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    • 1. 发明授权
    • Remapping of inoperable memory blocks
    • 重新映射不可操作的内存块
    • US09092357B2
    • 2015-07-28
    • US12915025
    • 2010-10-29
    • John D. DavisKarin StraussDouglas C. Burger
    • John D. DavisKarin StraussDouglas C. Burger
    • G06F13/00G06F13/28G06F12/10G06F12/02G11C13/00G11C29/00
    • G06F12/1027G06F12/0292G06F12/1009G06F2212/1044G06F2212/2024G11C13/0004G11C13/0035G11C29/76
    • Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table.
    • PCM设备中的不可操作的相变存储器(PCM)块被重新映射到一个或多个可操作的PCM块,例如。 通过维护不可操作的块表,其包括每个不可操作的PCM块的条目和重新映射的PCM块的地址。 或者,可以通过将重映射块的地址存储在块本身中来重新映射PCM块,并且设置指示块的重映射比特已被重新映射。 在由处理器执行重新映射的情况下,可以在转换旁边的缓冲器中设置不可操作的块位,缓冲器指示虚拟存储器页是否与不可操作或重新映射的PCM块相关联。 当接收到访问虚拟存储器页面的请求时,处理器引用与虚拟存储器页面相关联的不可操作块位,以确定是否检查不可操作块表中的重新映射的PCM块。
    • 2. 发明申请
    • REMAPPING OF INOPERABLE MEMORY BLOCKS
    • 重写无法记忆块
    • US20120110278A1
    • 2012-05-03
    • US12915025
    • 2010-10-29
    • John D. DavisKarin StraussDouglas C. Burger
    • John D. DavisKarin StraussDouglas C. Burger
    • G06F12/00
    • G06F12/1027G06F12/0292G06F12/1009G06F2212/1044G06F2212/2024G11C13/0004G11C13/0035G11C29/76
    • Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table.
    • PCM设备中的不可操作的相变存储器(PCM)块被重新映射到一个或多个可操作的PCM块,例如。 通过维护不可操作的块表,其包括每个不可操作的PCM块的条目和重新映射的PCM块的地址。 或者,可以通过将重映射块的地址存储在块本身中来重新映射PCM块,并且设置指示块的重映射比特已被重新映射。 在由处理器执行重新映射的情况下,可以在转换旁边的缓冲器中设置不可操作的块位,缓冲器指示虚拟存储器页是否与不可操作或重新映射的PCM块相关联。 当接收到访问虚拟存储器页面的请求时,处理器引用与虚拟存储器页面相关联的不可操作块位,以确定是否检查不可操作块表中的重新映射的PCM块。
    • 3. 发明申请
    • ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE
    • 用于非易失存储器的错误修正指针
    • US20110296258A1
    • 2011-12-01
    • US12788329
    • 2010-05-27
    • Stuart SchechterKarin StraussGabriel LohDouglas C. Burger
    • Stuart SchechterKarin StraussGabriel LohDouglas C. Burger
    • H03M13/05G06F11/00G06F11/10
    • G06F11/1048G11C13/0004H03M13/09H03M13/19
    • Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.
    • 使用存储器行实现错误校正指针(ECP)的架构,其指向故障存储器单元的地址,每个存储器单元与替换单元配对以替代故障单元。 如果数组中的两个纠错指针指向同一个单元格,则优先级规则将指定具有较高索引的数组条目(稍后创建的条目)优先。 为了对正在使用的纠错指针的数量进行计数,可以采用空指针地址来指示指针不活动,可以添加激活位,和/或计数器,其表示有效的纠错指针的数目 。 提供了用于纠错结构内的磨损均衡的机制,或者用于将该方案与用于可能发生瞬态故障的情况的单错误校正位配对。 该架构还使用指针来纠正易失性和非易失性存储器中的错误。
    • 4. 发明授权
    • Error correcting pointers for non-volatile storage
    • 错误纠正非易失性存储的指针
    • US08839053B2
    • 2014-09-16
    • US12788329
    • 2010-05-27
    • Stuart SchechterKarin StraussGabriel LohDouglas C. Burger
    • Stuart SchechterKarin StraussGabriel LohDouglas C. Burger
    • G11C29/00G06F11/10H03M13/09G11C13/00H03M13/19
    • G06F11/1048G11C13/0004H03M13/09H03M13/19
    • Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.
    • 使用存储器行实现错误校正指针(ECP)的架构,其指向故障存储器单元的地址,每个存储器单元与替换单元配对以替代故障单元。 如果数组中的两个纠错指针指向同一个单元格,则优先级规则将指定具有较高索引的数组条目(稍后创建的条目)优先。 为了对正在使用的纠错指针的数量进行计数,可以采用空指针地址来指示指针不活动,可以添加激活位和/或计数器,其表示活动的纠错指针的数目 。 提供了用于纠错结构内的磨损均衡的机制,或者用于将该方案与用于可能发生瞬态故障的情况的单错误校正位配对。 该架构还使用指针来纠正易失性和非易失性存储器中的错误。
    • 7. 发明申请
    • FLEXIBLE NOTIFICATION MECHANISM FOR USER-LEVEL INTERRUPTS
    • 用于用户级别中断的灵活通知机制
    • US20110040915A1
    • 2011-02-17
    • US12633034
    • 2009-12-08
    • Karin StraussJaewoong Chung
    • Karin StraussJaewoong Chung
    • G06F13/24
    • G06F13/26G06F9/4818G06F13/4022
    • A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system.
    • 一种方法包括根据从多个用户级中断传递配置中选择的用户级中断传送配置向一个或多个接收者传递指示用户级中断的用户级中断消息。 一个或多个接收者对应于在多核系统中的多个处理器核的一个或多个处理器核上执行的一个或多个应用线程。 一种方法包括根据失败的递送通知模式配置,生成用户级别中断的指示符,该用户级别中断无法传送给用户级中断消息的一个或多个预期接收者。 用户级中断可以由在多核系统中的多个处理器核的第一处理器核上执行的应用程序线程发出。
    • 8. 发明授权
    • Adaptive snoop-and-forward mechanisms for multiprocessor systems
    • 多处理器系统的自适应窥探和转发机制
    • US07437520B2
    • 2008-10-14
    • US11178924
    • 2005-07-11
    • Xiaowei ShenKarin Strauss
    • Xiaowei ShenKarin Strauss
    • G06F12/00
    • G06F12/0831G06F12/082G06F2212/507
    • In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be used to predict whether lazy forwarding or eager forwarding is used in processing the incoming cache request. With lazy forwarding, the node cannot forward the cache request to the subsequent node until the corresponding intra-node cache snoop operation is completed. With eager forwarding, the node can forward the cache request to the subsequent node immediately, before the corresponding intra-node cache snoop operation is completed. Furthermore, the snoop-and-forward prediction mechanism can be enhanced seamlessly with an appropriate snoop filter to avoid unnecessary intra-node cache snoop operations.
    • 在基于网络的高速缓存相关多处理器系统中,当节点接收到高速缓存请求时,节点可以执行节点内缓存侦听操作,并将缓存请求转发到网络中的后续节点。 可以使用侦听和转发预测机制来预测在处理传入缓存请求中是否使用惰性转发或热切换转发。 使用惰性转发,节点不能将缓存请求转发到后续节点,直到对应的节点内缓存侦听操作完成。 通过急切转发,节点可以在对应的节点内高速缓存监听操作完成之前立即将高速缓存请求转发到后续节点。 此外,可以与适当的窥探过滤器无缝地增强窥探和转发预测机制,以避免不必要的节点内缓存侦听操作。
    • 9. 发明授权
    • Progressive authentication
    • 逐行认证
    • US08839358B2
    • 2014-09-16
    • US13222538
    • 2011-08-31
    • Karin StraussOriana RivaDouglas BurgerJaron Lanier
    • Karin StraussOriana RivaDouglas BurgerJaron Lanier
    • G06F7/04G06F17/30
    • G06F21/31G06F21/40G06F2221/2101G06F2221/2113H04L63/08H04L2463/082
    • Progressive authentication is generally employed to establish the authenticity of a user, such as a user of a computing device, or a user that wants to access a proprietary data item, software application or on-line service. This can entail inputting authentication factors each of which corresponds to one or multiple attributes associated with the user, or historical patterns of one or more attributes associated with the user, or both, and a confidence level that estimates a reliability of the factor. Sensor readings captured by one or more sensors are also input. Each sensor senses a user attribute and are used to quantify each authentication factor confidence level. An overall confidence level is established based at least in part on a combination of the individual confidence levels. A user is then designated as being authentic whenever the established overall confidence level exceeds a prescribed authentication level. This process can be continuous with the overall confidence level being continually updated.
    • 通常采用逐行认证来建立用户(诸如计算设备的用户)或希望访问专有数据项,软件应用程序或在线服务的用户的真实性。 这可能需要输入每个对应于与用户相关联的一个或多个属性的认证因素,或与用户相关联的一个或多个属性的历史模式或两者,以及估计因子的可靠性的置信水平。 一个或多个传感器捕获的传感器读数也被输入。 每个传感器感测用户属性,并用于量化每个认证因子置信水平。 至少部分地基于个体置信水平的组合建立整体置信水平。 只要建立的总体置信水平超过规定的认证级别,用户被指定为是可信的。 这个过程可以持续,整体置信水平不断更新。