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1. 发明授权

US06998719B2 Power grid layout techniques on integrated circuits 有权
标题翻译：集成电路电网布局技术
公开(公告)号：US06998719B2
公开(公告)日：2006-02-14
申请号：US10631471
申请日：2003-07-30
申请人： John Campbell , Kim R. Stevens , Luigi DiGregorio
发明人： John Campbell , Kim R. Stevens , Luigi DiGregorio
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
摘要翻译：提供了用于减少通过在集成电路上布线导电迹线引入的电源电压降的技术。还提供了用于减少在集成电路的不同区域中接收的电源电压的变化的技术。电源电压在集成电路内跨导线。导电迹线耦合到从外部源接收电源电压的接合焊盘。迹线中的另一个接收高电源电压V DD和低电源电压V SS。导电迹线通过提供较短的路径将电源电压路由到集成电路上的电路元件来减小电源电压中的电压降。

2. 发明授权

US07462941B2 Power grid layout techniques on integrated circuits 有权
标题翻译：集成电路电网布局技术
公开(公告)号：US07462941B2
公开(公告)日：2008-12-09
申请号：US11237304
申请日：2005-09-27
申请人： John Campbell , Kim R. Stevens , Luigi DiGregorio
发明人： John Campbell , Kim R. Stevens , Luigi DiGregorio
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
摘要翻译：提供了用于减少通过在集成电路上布线导电迹线引入的电源电压降的技术。还提供了用于减少在集成电路的不同区域中接收的电源电压的变化的技术。电源电压在集成电路内跨导线。导电迹线耦合到从外部源接收电源电压的焊料凸块。迹线中的另一个接收高电源电压VDD和低电源电压VSS。导电迹线通过提供较短的路径将电源电压路由到集成电路上的电路元件来减小电源电压中的电压降。

3. 发明申请

US20050023705A1 Power grid layout techniques on integrated circuits 有权
标题翻译：集成电路电网布局技术
公开(公告)号：US20050023705A1
公开(公告)日：2005-02-03
申请号：US10631471
申请日：2003-07-30
申请人： John Campbell , Kim Stevens , Luigi DiGregorio
发明人： John Campbell , Kim Stevens , Luigi DiGregorio
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L23/528 , H01L27/04 , H01L23/48 , G06F17/50 , H01L29/40
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
摘要翻译：提供了用于减少通过在集成电路上布线导电迹线引入的电源电压降的技术。还提供了用于减少在集成电路的不同区域中接收的电源电压的变化的技术。电源电压在集成电路内跨导线。导电迹线耦合到从外部源接收电源电压的接合焊盘。迹线中的另一个接收高电源电压VDD和低电源电压VSS。导电迹线通过提供较短的路径将电源电压路由到集成电路上的电路元件来减小电源电压中的电压降。

4. 发明申请

US20060081984A1 Power grid layout techniques on integrated circuits 有权
标题翻译：集成电路电网布局技术
公开(公告)号：US20060081984A1
公开(公告)日：2006-04-20
申请号：US11237304
申请日：2005-09-27
申请人： John Campbell , Kim Stevens , Luigi DiGregorio
发明人： John Campbell , Kim Stevens , Luigi DiGregorio
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
摘要翻译：提供了用于减少通过在集成电路上布线导电迹线引入的电源电压降的技术。还提供了用于减少在集成电路的不同区域中接收的电源电压的变化的技术。电源电压在集成电路内跨导线。导电迹线耦合到从外部源接收电源电压的焊料凸块。迹线中的另一个接收高电源电压V DD和低电源电压V SS。导电迹线通过提供较短的路径将电源电压路由到集成电路上的电路元件来减小电源电压中的电压降。

5. 发明授权

US6046942A Output buffer including an application-specific SRAM memory cell for low voltage, high speed operation 有权
标题翻译：输出缓冲器包括用于低电压，高速运行的专用SRAM存储单元
公开(公告)号：US6046942A
公开(公告)日：2000-04-04
申请号：US157708
申请日：1998-09-21
申请人： Yi-Ren Warry Hwang , Luigi DiGregorio
发明人： Yi-Ren Warry Hwang , Luigi DiGregorio
IPC分类号： G11C11/41 , G11C11/412 , G11C11/419 , H03K3/037 , G11C16/04
CPC分类号： H03K3/037 , G11C11/41 , G11C11/412 , G11C11/419
摘要： An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transistor for coupling the third node to the power supply terminal in response to the read data line having a low logical value. In memory structures such as register files or arrays, the eighth and ninth transistors provide an output stage that can be shared by each memory cell coupled to the read data line.
摘要翻译：应用专用SRAM存储单元包括第一和第二交叉耦合的反相器，其耦合在第一和第二节点处，用于存储第一节点处的信息位和第二节点处的位的补码，第一和第二串联连接的晶体管，用于响应于写入地址信号和具有高逻辑值的时钟将写数据信号耦合到第一节点，用于响应于写数据信号将第二节点耦合到地的第三，第四和第五串联晶体管，写入地址信号和具有高逻辑值的时钟;第六晶体管，用于响应于具有高逻辑值的读地址信号将该位耦合到读数据线;第七晶体管，用于将该位的补码耦合到第三节点对具有高逻辑值的读地址信号的响应;第八晶体管，用于响应于具有低逻辑值的第三节点将读数据线耦合到电源端以及用于响应于具有低逻辑值的读取数据线将第三节点耦合到电源端子的第九晶体管。在诸如寄存器文件或阵列的存储器结构中，第八和第九晶体管提供可由耦合到读取数据线的每个存储器单元共享的输出级。

6. 发明授权

US5870331A Application-specific SRAM memory cell for low voltage, high speed operation 失效
标题翻译：专用SRAM存储单元用于低电压，高速运行
公开(公告)号：US5870331A
公开(公告)日：1999-02-09
申请号：US939016
申请日：1997-09-26
申请人： Yi-Ren Warry Hwang , Luigi DiGregorio
发明人： Yi-Ren Warry Hwang , Luigi DiGregorio
IPC分类号： G11C11/41 , G11C11/412 , G11C11/419 , H03K3/037 , G11C11/00
CPC分类号： H03K3/037 , G11C11/41 , G11C11/412 , G11C11/419
摘要： An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transistor for coupling the third node to the power supply terminal in response to the read data line having a low logical value. In memory structures such as register files or arrays, the eighth and ninth transistors provide an output stage that can be shared by each memory cell coupled to the read data line.
摘要翻译：应用专用SRAM存储单元包括第一和第二交叉耦合的反相器，其耦合在第一和第二节点处，用于存储第一节点处的信息位和第二节点处的位的补码，第一和第二串联连接的晶体管，用于响应于写入地址信号和具有高逻辑值的时钟将写数据信号耦合到第一节点，用于响应于写数据信号将第二节点耦合到地的第三，第四和第五串联晶体管，写入地址信号和具有高逻辑值的时钟;第六晶体管，用于响应于具有高逻辑值的读地址信号将该位耦合到读数据线;第七晶体管，用于将该位的补码耦合到第三节点对具有高逻辑值的读地址信号的响应;第八晶体管，用于响应于具有低逻辑值的第三节点将读数据线耦合到电源端以及用于响应于具有低逻辑值的读取数据线将第三节点耦合到电源端子的第九晶体管。在诸如寄存器文件或阵列的存储器结构中，第八和第九晶体管提供可由耦合到读取数据线的每个存储器单元共享的输出级。

7. 发明授权

US5774005A Latching methodology 失效
标题翻译：闭锁方法
公开(公告)号：US5774005A
公开(公告)日：1998-06-30
申请号：US706340
申请日：1996-08-30
申请人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi DiGregorio , Donald A. Draper
发明人： Hamid Partovi , Robert C. Burd , Udin Salim , Frederick Weber , Luigi DiGregorio , Donald A. Draper
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.
摘要翻译：高性能触发电路实现。触发器电路包括“隐式”单触发以产生延迟的时钟输出（407）。触发器包括耦合到时钟输入（210）的延迟块（405）。触发器可以是D型触发器。在触发器的正边沿触发实施例中，延迟时钟输出（407）的下降沿（540）在延迟时段（548）之后的时钟信号的上升沿（544）之后。触发器响应于在该延迟时段（548）期间的时钟输入（210）在数据输入端（205）处的新数据中的时钟。数据保存在存储块（450）中。触发器具有非常好的瞬态特性，特别是设置和时钟到输出时间。触发器不消耗静电。

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