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    • 3. 发明申请
    • DURABLE TRANSACTIONS WITH STORAGE-CLASS MEMORY
    • 具有存储级存储器的可执行交易
    • US20140075122A1
    • 2014-03-13
    • US13613704
    • 2012-09-13
    • Mohammad BanikazemiJohn Alan Bivens
    • Mohammad BanikazemiJohn Alan Bivens
    • G06F12/00
    • G06F11/00G06F9/467G06F12/0828G06F12/0891
    • A system for conducting memory transactions includes a non-volatile main memory and a memory buffer including a plurality of cache lines. Each of the cache lines includes content and one or more bits signifying whether a memory transaction corresponding to the content of the cache line has been performed to completion and whether the content of the cache line matches content of a corresponding location of the non-volatile main memory. When the one or more bits of a cache line of the plurality of cache lines signifies that the transaction has been performed to completion and the content of the cache line does not match the content of the corresponding location of the non-volatile memory, access to modify the content of the cache line is restricted until the content of the cache line is written to the corresponding location of the non-volatile main memory.
    • 用于进行存储器事务的系统包括非易失性主存储器和包括多个高速缓存行的存储器缓冲器。 每个高速缓存行包括内容以及表示与高速缓存行的内容相对应的存储器事务是否已执行完成的一个或多个位,以及高速缓存行的内容是否与非易失性主体的对应位置的内容相匹配 记忆。 当多个高速缓存行的高速缓存行的一个或多个位表示事务已被执行完成并且高速缓存行的内容与非易失性存储器的对应位置的内容不匹配时,访问 修改缓存行的内容受到限制,直到高速缓存行的内容被写入到非易失主存的相应位置。
    • 7. 发明授权
    • Durable and coherent cache transactions between volatile and non-volatile memories
    • 易失性和非易失性存储器之间的持久和一致的缓存事务
    • US09058244B2
    • 2015-06-16
    • US13613704
    • 2012-09-13
    • Mohammad BanikazemiJohn Alan Bivens
    • Mohammad BanikazemiJohn Alan Bivens
    • G06F12/00G06F11/00G06F12/08G06F9/46
    • G06F11/00G06F9/467G06F12/0828G06F12/0891
    • A system for conducting memory transactions includes a non-volatile main memory and a memory buffer including a plurality of cache lines. Each of the cache lines includes content and one or more bits signifying whether a memory transaction corresponding to the content of the cache line has been performed to completion and whether the content of the cache line matches content of a corresponding location of the non-volatile main memory. When the one or more bits of a cache line of the plurality of cache lines signifies that the transaction has been performed to completion and the content of the cache line does not match the content of the corresponding location of the non-volatile memory, access to modify the content of the cache line is restricted until the content of the cache line is written to the corresponding location of the non-volatile main memory.
    • 用于进行存储器事务的系统包括非易失性主存储器和包括多个高速缓存行的存储器缓冲器。 每个高速缓存行包括内容以及表示与高速缓存行的内容相对应的存储器事务是否已执行完成的一个或多个位,以及高速缓存行的内容是否与非易失性主体的对应位置的内容相匹配 记忆。 当多个高速缓存行的高速缓存行的一个或多个位表示事务已被执行完成并且高速缓存行的内容与非易失性存储器的对应位置的内容不匹配时,访问 修改缓存行的内容受到限制,直到高速缓存行的内容被写入到非易失主存的相应位置。
    • 8. 发明申请
    • DURABLE TRANSACTIONS WITH STORAGE-CLASS MEMORY
    • 具有存储级存储器的可执行交易
    • US20140075086A1
    • 2014-03-13
    • US13614735
    • 2012-09-13
    • Mohammad BanikazemiJohn Alan Bivens
    • Mohammad BanikazemiJohn Alan Bivens
    • G06F12/02
    • G06F11/00G06F9/467G06F12/0828G06F12/0891
    • A method for conducting memory transactions includes receiving a transaction. The steps of the received transaction are performed in a memory buffer. A state of the memory buffer cache lines is set as pending and unstored while the transaction is in progress. After all steps have been successfully performed, the state of the memory buffer cache lines are changed to complete and unstored. When it is determined that the memory buffer cache lines are to be written to the non-volatile main memory, the contents is written to the non-volatile main memory. The state of the memory buffer cache lines are then changed to complete and stored. When the memory buffer cache lines are in the complete and unstored state, access to modify their content is restricted.
    • 用于执行存储器事务的方法包括接收事务。 接收的事务的步骤在存储器缓冲器中执行。 内存缓冲区高速缓存行的状态在事务进行中被设置为挂起状态和未挂起状态。 在所有步骤成功执行之后,内存缓冲区高速缓存行的状态将更改为完成和未归档。 当确定要将内存缓冲器高速缓存行写入非易失性主存储器时,将内容写入非易失性主存储器。 然后更改内存缓冲区高速缓存行的状态以完成并存储。 当内存缓冲区高速缓存行处于完全状态并且不存在状态时,修改其内容的访问受到限制。