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1. 发明授权

US07233810B2 Dynamically reconfigurable universal transmitter system 有权
标题翻译：动态可重配置通用发射机系统
公开(公告)号：US07233810B2
公开(公告)日：2007-06-19
申请号：US09922484
申请日：2001-08-03
申请人： Joel D. Medlock , Uma Jha , David M. Holmes , Andrea Y. J. Chen , Madasamy Kartheepan
发明人： Joel D. Medlock , Uma Jha , David M. Holmes , Andrea Y. J. Chen , Madasamy Kartheepan
IPC分类号： H04B1/38
CPC分类号： H04B1/04 , H04B1/38 , H04B1/406 , H04B7/06 , H04W72/1215 , H04W88/02 , H04W88/06 , Y10S707/99953 , Y10S707/99955
摘要： A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.
摘要翻译：本文公开了一种动态可重新配置的通用发射机系统。电子设备包括用于产生传输信号的多个发射机资源，输出总线和耦合到输出总线的天线加法器。输出总线选择性地耦合到多个发射机资源，并且其选择性地接收来自多个传输资源的传输信号。天线夏天存储在输出总线上接收的发送信号。

2. 发明授权

US08515352B2 Dynamically reconfigurable universal transmitter system 有权
公开(公告)号：US08515352B2
公开(公告)日：2013-08-20
申请号：US11748311
申请日：2007-05-14
申请人： Joel D. Medlock , Uma Jha , David M. Holmes , Andrea Y. J. Chen , Madasamy Kartheepan
发明人： Joel D. Medlock , Uma Jha , David M. Holmes , Andrea Y. J. Chen , Madasamy Kartheepan
IPC分类号： H04B1/00 , H04K3/00
CPC分类号： H04B1/04 , H04B1/38 , H04B1/406 , H04B7/06 , H04W72/1215 , H04W88/02 , H04W88/06 , Y10S707/99953 , Y10S707/99955
摘要： A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

3. 发明授权

US06393512B1 Circuit and method for detecting bank conflicts in accessing adjacent banks 有权
标题翻译：检测相邻银行的银行冲突的电路和方法
公开(公告)号：US06393512B1
公开(公告)日：2002-05-21
申请号：US09407224
申请日：1999-09-27
申请人： Andrea Y. J. Chen , Lordson L. Yue
发明人： Andrea Y. J. Chen , Lordson L. Yue
IPC分类号： G06F1200
CPC分类号： G06F13/1647
摘要： A bank conflict detector compares at least a portion of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists. Otherwise, the bank conflict detector compares at least one of the addresses (both addresses in one implementation) with one or more predetermined patterns (e.g. two patterns in one implementation), and in case of a match determines that a bank conflict exists, and otherwise determines that no bank conflict exists. These patterns also have 0s in the least significant positions and 1s in the most significant positions or vice versa, depending on the implementation.
摘要翻译：银行冲突检测器将当前地址信号的至少一部分（即，由当前发送到主存储器的请求产生的地址信号）与待发布的存储器地址信号的相应部分进行比较，以确定是否存在冲突存在具体来说，在一个实施例中，存储体冲突检测器包括多个异或门，其接收要比较的两个地址作为输入，并产生与预定模式进行比较的输出（也称为“异或结果”），以确定是否存在银行冲突。例如，如果存储体冲突检测器发现XOR结果为0（零），则两个地址访问同一个存储区。银行冲突检测器还具有由最低有效位中的多个连续1形成的模式和最高有效位中的多个连续0的XOR结果。如果没有匹配，则银行冲突检测器确定不存在银行冲突。否则，银行冲突检测器将至少一个地址（一个实现中的两个地址）与一个或多个预定模式（例如，一个实现中的两个模式）进行比较，并且在匹配的情况下确定存在银行冲突，否则决定不存在银行冲突。这些模式在最低有效位置也有0，在最重要的位置也有1，反之亦然，这取决于实现。

4. 发明授权

US06507886B1 Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory 有权
公开(公告)号：US06507886B1
公开(公告)日：2003-01-14
申请号：US09847914
申请日：2001-05-01
申请人： Andrea Y. J. Chen , Lordson L. Yue
发明人： Andrea Y. J. Chen , Lordson L. Yue
IPC分类号： G06F1200
CPC分类号： G06F13/1631
摘要： A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit. Such prioritization of requests can be made programmable, depending on signals held in storage elements that are included in the main memory scheduler.

5. 发明授权

US06393534B1 Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory 有权
标题翻译：调度程序，用于避免在向主内存发出并发请求时发生冲突
公开(公告)号：US06393534B1
公开(公告)日：2002-05-21
申请号：US09407131
申请日：1999-09-27
申请人： Andrea Y. J. Chen , Lordson L. Yue
发明人： Andrea Y. J. Chen , Lordson L. Yue
IPC分类号： G06F1200
CPC分类号： G06F13/1631
摘要： A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit. Such prioritization of requests can be made programmable, depending on signals held in storage elements that are included in the main memory scheduler.
摘要翻译：主存储器调度器包括存储器，并且存储访问主存储器的请求（诸如读请求，写请求或刷新请求）。通常，主存储器调度器以与接收请求的顺序不同的顺序来发布从存储器到主存储器的请求，例如以避免存储体冲突。在该示例中，主存储器调度器向第一存储器发出第一请求，该第一存储器在发出第二存储器之前不是与第二存储器组（即当前被访问的）相一致请求到与第二存储体（或相邻）第二存储体一致的存储体。此外，即使最近接收到刷新请求，主存储器调度器在发出读取请求或写入请求之前发出刷新请求，从而在读取和写入请求之前优先刷新请求。类似地，主存储器调度器在写入请求之前优先考虑大部分读取请求，使得发起读取请求的处理器通常不被先前发出的写入请求所阻止，如先前先出（FIFO）发出内存请求。主存储器调度器执行FIFO处理，例如，当稍后接收的读请求和较早接收到的写请求都访问主存储器中的相同位置时，或者当待处理写请求的数量超过预定限制时。可以根据包含在主存储器调度器中的存储元件中保存的信号，使这些请求优先化可编程。

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