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1. 发明授权

US08209562B2 Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals 有权
标题翻译：双数据速率转换器电路包括用于提供多个时钟相位信号的延迟锁定环
公开(公告)号：US08209562B2
公开(公告)日：2012-06-26
申请号：US12684026
申请日：2010-01-07
申请人： Jody Defazio , Oswald Becca , Peter Nyasulu
发明人： Jody Defazio , Oswald Becca , Peter Nyasulu
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1066 , G11C7/222 , G11C11/41 , G11C2029/5602
摘要： In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
摘要翻译：在存储器接口中，将延迟锁定环（DLL）添加到系统中，以便将驱动时钟的精确的PVT不敏感转换提供给写入数据眼睛。将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。该系统允许在时钟占空比上更加宽松的约束。固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实现的便利性和易于重用。

2. 发明授权

US6087875A Single-edge adjustable delay circuit 失效
标题翻译：单边可调延时电路
公开(公告)号：US6087875A
公开(公告)日：2000-07-11
申请号：US31732
申请日：1998-02-27
申请人： Jody Defazio
发明人： Jody Defazio
IPC分类号： H03K5/133 , H03K5/13
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00195
摘要： In accordance with this invention there is provided a circuit for delaying a selected edge of an input signal for use in a deep sub-micron process semiconductor device, the circuit comprising an inverter element having an input and output node, a load element comprising resistive and capacitive (RC) elements a first transistor element, coupled to the RC load element and selectively operable to couple the RC element to the output node upon receipt of the selected edge of the input signal and for decoupling the RC element from the output node upon receipt of an opposite edge of the input signal, whereby a delay is introduced by the load element on the selected edge of the input signal with little negative effect on the opposite edge of the input signal.
摘要翻译：根据本发明，提供了一种用于延迟用于深亚微米工艺半导体器件的输入信号的选定边缘的电路，该电路包括具有输入和输出节点的反相器元件，负载元件包括电阻和电容（RC）元件，第一晶体管元件，耦合到所述RC负载元件，并且可选地可操作以在接收到所述输入信号的选定边缘时将所述RC元件耦合到所述输出节点，以及用于在接收到所述RC元件时从所述输出节点解耦RC元件输入信号的相对边缘，由此负载元件在输入信号的选定边缘上引入延迟，对输入信号的相对边缘几乎没有负面影响。

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