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1. 发明申请

US20100122104A1 APPARATUS AND METHOD FOR INTERFACING TO A MEMORY 有权
标题翻译：用于连接到存储器的装置和方法
公开(公告)号：US20100122104A1
公开(公告)日：2010-05-13
申请号：US12684026
申请日：2010-01-07
申请人： Jody DEFAZIO , Oswald BECCA , Peter NYASULU
发明人： Jody DEFAZIO , Oswald BECCA , Peter NYASULU
IPC分类号： G06F1/12 , G06F1/06 , G06F1/10
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1066 , G11C7/222 , G11C11/41 , G11C2029/5602
摘要： In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
摘要翻译：在存储器接口中，将延迟锁定环（DLL）添加到系统中，以便将驱动时钟的精确的PVT不敏感转换提供给写入数据眼睛。将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。该系统允许在时钟占空比上更加宽松的约束。固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实现的便利性和易于重用。

2. 发明申请

US20070283182A1 APPARATUS AND METHOD FOR INTERFACING TO A MEMORY 有权
标题翻译：用于连接到存储器的装置和方法
公开(公告)号：US20070283182A1
公开(公告)日：2007-12-06
申请号：US11536709
申请日：2006-09-29
申请人： Jody DEFAZIO , Oswald BECCA , Peter NYASULU
发明人： Jody DEFAZIO , Oswald BECCA , Peter NYASULU
IPC分类号： G06F1/00
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1066 , G11C7/222 , G11C11/41 , G11C2029/5602
摘要： A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
摘要翻译：将延迟锁定环（DLL）添加到系统中，以便将写入数据眼中的驱动时钟的精确的PVT不敏感转换提供给系统。将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。该系统允许在时钟占空比上更加宽松的约束。固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实施的便利性和易于重用。

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