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    • 5. 发明申请
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US20060279331A1
    • 2006-12-14
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/00
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。
    • 6. 发明授权
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US07385422B2
    • 2008-06-10
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/02
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。
    • 7. 发明申请
    • Frame-shifted backlight-scaled display system and frame-shifted backlight scaling method
    • 帧移背光显示系统和帧移背光缩放方法
    • US20090015543A1
    • 2009-01-15
    • US12216720
    • 2008-07-10
    • Wei-Hsin WeiJing-Meng Liu
    • Wei-Hsin WeiJing-Meng Liu
    • G09G3/36
    • G09G3/3406G09G2320/0646G09G2330/021G09G2340/16
    • In a backlight scaling method and system, the pixel values of a first frame are counted to obtain a first histogram of this frame simultaneously when the first frame is inputted to the data driver ICs, and a first backlight luminance generated according to the first histogram is applied to the backlight driver for the backlight scaling for a second frame when the derived second frame is inputted to the data driver after the pixel values of the second frame is recalculated by the first backlight luminance. In the same way, when the derived second frame is inputted to the data driver, the original pixel values of the second frame are counted to obtain a second histogram of this frame and to generate a second backlight luminance for the third frame, and so on. Because the backlight luminance for each frame is generated according to the histogram of the previous frame, only small amount of pixel buffers for the processing is required.
    • 在背光缩放方法和系统中,当第一帧被输入到数据驱动器IC时,对第一帧的像素值进行计数以同时获得该帧的第一直方图,并且根据第一直方图生成的第一背光亮度为 当在第二帧的像素值被第一背光亮度重新计算之后,当所导出的第二帧被输入到数据驱动器时,应用于用于第二帧的背光缩放的背光驱动器。 以相同的方式,当将导出的第二帧输入到数据驱动器时,对第二帧的原始像素值进行计数以获得该帧的第二直方图,并产生第三帧的第二背光亮度,等等 。 由于根据前一帧的直方图产生每帧的背光亮度,因此仅需要少量用于处理的像素缓冲器。
    • 10. 发明授权
    • Output control apparatus of pulse width modulator
    • 脉宽调制器输出控制装置
    • US06803798B1
    • 2004-10-12
    • US10639503
    • 2003-08-13
    • Wei-Hsin WeiSheng-Yi HoJung-Lin Chang
    • Wei-Hsin WeiSheng-Yi HoJung-Lin Chang
    • H03K502
    • H03F3/217H03G3/00H03G3/3021
    • The invention provides an output control apparatus for adjusting the output level of a pulse width modulation (PWM) signal by changing the amplitude level of the output PWM signal. The output control apparatus comprises a control signal generator, a digital-to-analog converter (DAC), and an output circuit. The control signal generator generates a digital control signal. The DAC outputs a predetermined level according to the digital control signal. The output circuit with a negative feedback loop receives the PWM signal and receives the predetermined level by the negative feedback loop. While the PWM signal is logic number “0”, the negative feedback loop is not switched on, so as to control the level of the PWM signal at a base level. While the PWM signal is logic number “1”, the negative feedback loop is switched on, so as to control the level of the PWM signal at the predetermined level.
    • 本发明提供一种输出控制装置,用于通过改变输出PWM信号的幅度电平来调节脉宽调制(PWM)信号的输出电平。 输出控制装置包括控制信号发生器,数模转换器(DAC)和输出电路。 控制信号发生器产生数字控制信号。 DAC根据数字控制信号输出预定电平。 具有负反馈回路的输出电路接收PWM信号并通过负反馈回路接收预定电平。 当PWM信号为逻辑编号“0”时,负反馈环路不接通,以便控制基准电平的PWM信号电平。 当PWM信号为逻辑编号“1”时,负反馈环路导通,以便将PWM信号的电平控制在预定电平。