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1. 发明申请

US20140189469A1 Nonvolatile Memory Devices with Age-Based Variability of Read Operations and Methods of Operating Same 有权
标题翻译：具有基于年龄的读取操作的可变性的非易失性存储器件和操作方法相同
公开(公告)号：US20140189469A1
公开(公告)日：2014-07-03
申请号：US14201170
申请日：2014-03-07
申请人： JinHyeok Choi , Hwaseok Oh
发明人： JinHyeok Choi , Hwaseok Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1072 , G06F11/1048 , G11C16/349
摘要： Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable.
摘要翻译：集成电路存储器系统和方法包括：将与读取请求相对应的存储器块的擦除次数与第一值进行比较，并且根据与第一可靠性改进操作相对应的第一读取条件来读取存储在存储器块中的数据，的擦除周期小于第一个值。当根据第一读取条件读取的数据的错误是可校正时，可以使用纠错码（ECC）来校正根据第一读取条件读取的数据的错误。

2. 发明申请

US20110209032A1 Nonvolatile Memory Devices with Age-Based Variability of Read Operations and Methods of Operating Same 有权
标题翻译：具有基于年龄的读取操作的可变性的非易失性存储器件和操作方法相同
公开(公告)号：US20110209032A1
公开(公告)日：2011-08-25
申请号：US13033276
申请日：2011-02-23
申请人： JinHyeok Choi , Hwaseok Oh
发明人： JinHyeok Choi , Hwaseok Oh
IPC分类号： G06F11/10 , G11C16/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C16/349
摘要： Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.
摘要翻译：集成电路存储器系统包括其中具有非易失性存储器单元的阵列的非易失性存储器件以及电耦合到非易失性存储器件的存储器控制器。存储器控制器被配置为将信号施加到非易失性存储器件，使得非易失性存储器件修改如何从非易失性存储器单元阵列中读取数据。响应于检测到非易失性存储器件的年龄增加而发生该修改。可以通过保持非易失性存储器件已经经历了编程/擦除周期的次数来确定非易失性存储器件的时代。

3. 发明授权

US09262266B2 Nonvolatile memory devices with age-based variability of read operations and methods of operating same 有权
标题翻译：非易失性存储器件，具有基于年龄的读取操作的可变性和操作方法
公开(公告)号：US09262266B2
公开(公告)日：2016-02-16
申请号：US14201170
申请日：2014-03-07
申请人： JinHyeok Choi , Hwaseok Oh
发明人： JinHyeok Choi , Hwaseok Oh
IPC分类号： G11C29/00 , G06F11/10 , G11C16/34
CPC分类号： G06F11/1072 , G06F11/1048 , G11C16/349
摘要： Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable.
摘要翻译：集成电路存储器系统和方法包括：将与读取请求相对应的存储器块的擦除次数与第一值进行比较，并且根据与第一可靠性改进操作相对应的第一读取条件来读取存储在存储器块中的数据，的擦除周期小于第一个值。当根据第一读取条件读取的数据的错误是可校正时，可以使用纠错码（ECC）来校正根据第一读取条件读取的数据的错误。

4. 发明申请

US20100064200A1 MEMORY SYSTEM AND DATA PROCESSING METHOD THEREOF 有权
标题翻译：存储器系统及其数据处理方法
公开(公告)号：US20100064200A1
公开(公告)日：2010-03-11
申请号：US12512097
申请日：2009-07-30
申请人： JinHyeok Choi , Hwaseok Oh , Jong-uk Song
发明人： JinHyeok Choi , Hwaseok Oh , Jong-uk Song
IPC分类号： G06F11/10 , G06F12/14
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2211/5646
摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.
摘要翻译：一种包括闪速存储器的存储器系统的数据处理方法，其包括判断最初从闪速存储器的选定页面读取的数据是否可校正。如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

5. 发明授权

US08694852B2 Nonvolatile memory devices with age-based variability of read operations and methods of operating same 有权
标题翻译：非易失性存储器件，具有基于年龄的读取操作的可变性和操作方法
公开(公告)号：US08694852B2
公开(公告)日：2014-04-08
申请号：US13033276
申请日：2011-02-23
申请人： JinHyeok Choi , Hwaseok Oh
发明人： JinHyeok Choi , Hwaseok Oh
IPC分类号： H03M13/00
CPC分类号： G06F11/1072 , G06F11/1048 , G11C16/349
摘要： Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.
摘要翻译：集成电路存储器系统包括其中具有非易失性存储器单元的阵列的非易失性存储器件以及电耦合到非易失性存储器件的存储器控制器。存储器控制器被配置为将信号施加到非易失性存储器件，使得非易失性存储器件修改如何从非易失性存储器单元阵列中读取数据。响应于检测到非易失性存储器件的年龄增加而发生该修改。可以通过保持非易失性存储器件已经经历了编程/擦除周期的次数来确定非易失性存储器件的时代。

6. 发明授权

US08365030B1 Nonvolatile memory devices and error correction methods thereof 有权
标题翻译：非易失性存储器件及其纠错方法
公开(公告)号：US08365030B1
公开(公告)日：2013-01-29
申请号：US12662016
申请日：2010-03-29
申请人： JinHyeok Choi , Hwaseok Oh
发明人： JinHyeok Choi , Hwaseok Oh
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A method for correcting read data error of a nonvolatile memory device, the error correction method including performing a first read operation of applying a first non-selection read voltage to a plurality of unselected memory cells to read a plurality of selected memory cells, performing a second read operation of applying a second non-selection read voltage less than the first non-selection read voltage to the unselected memory cells to read the selected memory cells, and comparing data sensed in the first and second read operations to detect error locations of read data.
摘要翻译：一种用于校正非易失性存储器件的读取数据错误的方法，所述纠错方法包括执行将第一非选择读取电压施加到多个未选择的存储器单元以读取多个选择的存储单元的第一读取操作，执行第二读取操作，将小于第一非选择读取电压的第二非选择读取电压施加到未选择的存储器单元以读取所选择的存储器单元，以及比较在第一和第二读取操作中感测的数据以检测读取的错误位置数据。

7. 发明授权

US08230303B2 Memory system and data processing method thereof 有权
标题翻译：存储系统及其数据处理方法
公开(公告)号：US08230303B2
公开(公告)日：2012-07-24
申请号：US12512097
申请日：2009-07-30
申请人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
发明人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2211/5646
摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.
摘要翻译：一种包括闪速存储器的存储器系统的数据处理方法，其包括判断从闪速存储器的选定页面开始读取的数据是否可校正。如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

8. 发明授权

US09515686B2 Signal transmitting circuit using common clock, and storage device therewith 有权
标题翻译：使用公共时钟的信号发送电路及其存储装置
公开(公告)号：US09515686B2
公开(公告)日：2016-12-06
申请号：US14822003
申请日：2015-08-10
申请人： Sung-Ha Kim , Sanghune Park , Hwaseok Oh
发明人： Sung-Ha Kim , Sanghune Park , Hwaseok Oh
IPC分类号： H04B1/04 , H03M9/00 , G06F13/40
CPC分类号： H04B1/0483 , G06F13/40 , G06F13/4291 , H03M9/00 , Y02D10/14 , Y02D10/151
摘要： A transmitting circuit includes a plurality of transmitters, an operation clock generator, and a clock divider. Each of the transmitters outputs data serially. The operation clock generator generates an operation clock signal. The clock divider divides the operation clock signal to generate a symbol clock signal. The plurality of transmitters receives the operation clock signal and the symbol clock signal in common. A clock signal provided to one transmitter is equally synchronized with a clock signal provided to other transmitter(s).
摘要翻译：发射电路包括多个发射机，操作时钟发生器和时钟分频器。每个发射机串行输出数据。操作时钟发生器产生操作时钟信号。时钟分频器分频操作时钟信号以产生符号时钟信号。多个发射机共同接收操作时钟信号和符号时钟信号。提供给一个发射机的时钟信号与提供给其它发射机的时钟信号同步。

9. 发明授权

US09571098B2 Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith 有权
标题翻译：信号接收电路包括具有可调电阻值的终端电阻，其操作方法和与其的存储装置
公开(公告)号：US09571098B2
公开(公告)日：2017-02-14
申请号：US14822074
申请日：2015-08-10
申请人： Sung-Ha Kim , Hwaseok Oh
发明人： Sung-Ha Kim , Hwaseok Oh
IPC分类号： H03K19/00 , H04B1/04
CPC分类号： H03K19/0005 , H03F1/3223 , H03F3/24 , H04B1/0475 , H04B1/0483 , H04B2001/0441
摘要： A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals.
摘要翻译：接收电路包括终端电阻电路和电阻调节电路。终端电阻电路被配置为经由第二输入端子经由第一输入端子和第二差分信号接收第一差分信号，并且被选择性地连接到第一和第二输入端子。终端电阻电路具有可调电阻值。电阻调整电路被配置为响应于信号接收准备命令和终端电阻电路与第一和第二输入端子的连接而减小终端电阻电路的电阻值。

10. 发明授权

US09373406B2 Flash memory based on storage devices and methods of operation 有权
标题翻译：基于存储设备的闪存和操作方法
公开(公告)号：US09373406B2
公开(公告)日：2016-06-21
申请号：US14299464
申请日：2014-06-09
申请人： Youngwook Kim , Hwaseok Oh , Soonbok Jang , Ji-Seung Youn
发明人： Youngwook Kim , Hwaseok Oh , Soonbok Jang , Ji-Seung Youn
IPC分类号： G11C7/00 , G11C16/26 , G11C7/10 , G11C7/22 , G11C16/32 , G06F13/16
CPC分类号： G11C16/26 , G06F13/1689 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C16/32
摘要： A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse width of the resulting cycle-controlled data strobe signal is greater than a pulse width of the data strobe signal.
摘要翻译：在读取数据传送期间，一种方法将从闪速存储器读取的数据相对于数据选通信号同步地传送到控制器。在读取数据传输周期的初始控制周期期间，扩展数据选通信号的周期，使得所得到的周期控制数据选通信号的脉冲宽度大于数据选通信号的脉冲宽度。

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