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1. 发明授权

US07636265B2 Flash memory device capable of reduced programming time 失效
标题翻译：闪存设备能够减少编程时间
公开(公告)号：US07636265B2
公开(公告)日：2009-12-22
申请号：US11264168
申请日：2005-11-02
申请人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
发明人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C16/3404
摘要： A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.
摘要翻译：提供了一种闪存器件，其包括适于将具有目标电压的编程电压提供给所选字线的高压发生器电路。闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。还提供了一种用于操作闪速存储器件的方法。

2. 发明授权

US07372754B2 Method and apparatus for controlling slope of word line voltage in nonvolatile memory device 有权
标题翻译：用于控制非易失性存储器件中字线电压斜率的方法和装置
公开(公告)号：US07372754B2
公开(公告)日：2008-05-13
申请号：US11354917
申请日：2006-02-16
申请人： Sang-Won Hwang , Jin-Wook Lee
发明人： Sang-Won Hwang , Jin-Wook Lee
IPC分类号： G11C7/00
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/30 , G11C16/32
摘要： A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.
摘要翻译：非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

3. 发明授权

US08321765B2 Method of reading data in non-volatile memory device 有权
标题翻译：在非易失性存储器件中读取数据的方法
公开(公告)号：US08321765B2
公开(公告)日：2012-11-27
申请号：US12702481
申请日：2010-02-09
申请人： Jin-Wook Lee , Sang-Won Hwang
发明人： Jin-Wook Lee , Sang-Won Hwang
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/26 , H03M13/15 , H03M13/1515 , H03M13/19
摘要： In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.
摘要翻译：在从非易失性存储器件读取数据的方法中，基于字线电压生成读取数据。读取数据包括从包括在非易失性存储器件中的多个扇区读取的数据。基于读取数据和坏扇区信息传输数据不良扇区数据。坏扇区数据对应于从包括在多个扇区中的至少一个坏扇区读取的数据。通过检查坏扇区数据的错误位来更新坏扇区信息。基于更新的坏扇区信息生成字线电压。

4. 发明授权

US07817473B2 Flash memory device with split string selection line structure 有权
标题翻译：闪存设备具有分割字符串选择线结构
公开(公告)号：US07817473B2
公开(公告)日：2010-10-19
申请号：US12014902
申请日：2008-01-16
申请人： Jin-Wook Lee , Sang-Won Hwang
发明人： Jin-Wook Lee , Sang-Won Hwang
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/3427
摘要： A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and a ground select transistor. The flash memory device also includes a plurality of string selection lines, wherein each one of the plurality of string selection lines is respectively connected to string select transistors associated the plurality of strings in one of the plurality of sectors.
摘要翻译：闪存器件被公开并且包括包括多个扇区的存储单元阵列。多个扇区中的每一个包括多个串，并且多个串中的每一个包括连接在串选择晶体管和接地选择晶体管之间的多个存储单元串联。闪存装置还包括多个串选择线，其中多个串选择线中的每一个分别连接到与多个扇区中的一个扇区中的多个扇区中的多个字符串相关联的串选择晶体管。

5. 发明申请

US20100211852A1 METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE 有权
标题翻译：在非易失性存储器件中读取数据的方法
公开(公告)号：US20100211852A1
公开(公告)日：2010-08-19
申请号：US12702481
申请日：2010-02-09
申请人： Jin-Wook Lee , Sang-Won Hwang
发明人： Jin-Wook Lee , Sang-Won Hwang
IPC分类号： H03M13/05 , G11C16/04 , G11C16/06 , G06F11/10 , H03M13/19 , H03M13/07
CPC分类号： G06F11/1068 , G11C16/26 , H03M13/15 , H03M13/1515 , H03M13/19
摘要： In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.
摘要翻译：在从非易失性存储器件读取数据的方法中，基于字线电压生成读取数据。读取数据包括从包括在非易失性存储器件中的多个扇区读取的数据。基于读取数据和坏扇区信息传输数据不良扇区数据。坏扇区数据对应于从包括在多个扇区中的至少一个坏扇区读取的数据。通过检查坏扇区数据的错误位来更新坏扇区信息。基于更新的坏扇区信息生成字线电压。

6. 发明申请

US20070025155A1 Method and apparatus for controlling slope of word line voltage in nonvolatile memory device 有权
标题翻译：用于控制非易失性存储器件中字线电压斜率的方法和装置
公开(公告)号：US20070025155A1
公开(公告)日：2007-02-01
申请号：US11354917
申请日：2006-02-16
申请人： Sang-Won Hwang , Jin-Wook Lee
发明人： Sang-Won Hwang , Jin-Wook Lee
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/30 , G11C16/32
摘要： A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.
摘要翻译：非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

7. 发明申请

US20060279994A1 Flash memory device capable of reduced programming time 失效
公开(公告)号：US20060279994A1
公开(公告)日：2006-12-14
申请号：US11264168
申请日：2005-11-02
申请人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
发明人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
IPC分类号： G11C16/04
CPC分类号： G11C16/3404
摘要： A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

8. 发明授权

US07974128B2 Flash memory device capable of reduced programming time 失效
标题翻译：闪存设备能够减少编程时间
公开(公告)号：US07974128B2
公开(公告)日：2011-07-05
申请号：US12620758
申请日：2009-11-18
申请人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
发明人： Min-Gun Park , Jin-Wook Lee , Sang-Won Hwang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3404
摘要： A flash memory device including a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.
摘要翻译：提供了一种包括适于向所选字线提供具有目标电压的编程电压的高压发生器电路的闪速存储器件。闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。还提供了一种用于操作闪速存储器件的方法。

9. 发明申请

US20140211565A1 METHODS OF PROGRAMMING MULTI-LEVEL CELL NONVOLATILE MEMORY DEVICES AND DEVICES SO OPERATING 有权
标题翻译：编程多级细胞非易失性存储器件的方法和操作的器件
公开(公告)号：US20140211565A1
公开(公告)日：2014-07-31
申请号：US14165835
申请日：2014-01-28
申请人： Jung-Ho Song , Su-Yong Kim , Sang-Won Hwang
发明人： Jung-Ho Song , Su-Yong Kim , Sang-Won Hwang
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
摘要： To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.
摘要翻译：在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

10. 发明授权

US08446776B2 Method of programming memory cells for a non-volatile memory device 有权
标题翻译：为非易失性存储器件编程存储器单元的方法
公开(公告)号：US08446776B2
公开(公告)日：2013-05-21
申请号：US13022688
申请日：2011-02-08
申请人： Sang-Won Hwang , Chan-Ho Kim
发明人： Sang-Won Hwang , Chan-Ho Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3454
摘要： A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.
摘要翻译：提供了一种用于非易失性存储器件的存储器单元的编程方法。该方法包括基于编程电压，第一验证电压和第二验证电压来执行增量步进脉冲程序（ISPP）操作，并且基于存储器的第一通过失败结果来改变编程电压的增量值基于第一验证电压产生第一通过失败结果。基于存储单元的第二通过失败结果完成ISPP操作，基于第二验证电压生成第二通过失败结果。

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