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1. 发明申请

US20180158912A1 MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application 审中-公开
公开(公告)号：US20180158912A1
公开(公告)日：2018-06-07
申请号：US15724989
申请日：2016-04-27
申请人： Jin-woo HAN , Yuniarto WIDJAJA , Zvi OR-BACH , Dinesh MAHESHWARI , Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Yuniarto Widjaja , Zvi Or-Bach , Dinesh Maheshwari
IPC分类号： H01L29/10 , H01L29/08 , H01L29/423 , H01L27/02 , H01L27/092 , G11C16/10 , G11C16/26 , H01L27/24 , H01L29/78 , H01L29/788 , H01L29/792
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

2. 发明授权

US10553683B2 MOSFET and memory cell having improved drain current through back bias application 有权
公开(公告)号：US10553683B2
公开(公告)日：2020-02-04
申请号：US15724989
申请日：2016-04-27
申请人： Jin-Woo Han , Yuniarto Widjaja , Zvi Or-Bach , Dinesh Maheshwari , Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Yuniarto Widjaja , Zvi Or-Bach , Dinesh Maheshwari
IPC分类号： H01L29/10 , H01L29/78 , H01L29/08 , H01L29/423 , H01L27/02 , H01L27/092 , G11C16/10 , G11C16/26 , H01L27/24 , H01L27/12 , H01L29/788 , H01L29/792 , H01L29/32 , H01L21/265 , H03K19/20 , H03K19/21 , H01L29/06 , H03K19/0948 , G11C16/04 , G11C13/00
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

3. 发明申请

US20140252451A1 MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR 有权
标题翻译：包含电浮标体晶体管的存储器件
公开(公告)号：US20140252451A1
公开(公告)日：2014-09-11
申请号：US14203235
申请日：2014-03-10
申请人： Jin-Woo Han , Yuniarto Widjaja
发明人： Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L29/792
CPC分类号： H01L27/10802 , G11C11/404 , G11C11/407 , G11C16/00 , G11C16/0416 , H01L29/0649 , H01L29/7841
摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
摘要翻译：一种包括电浮体的半导体存储单元。提供了一种操作存储单元的方法。

4. 发明申请

US20130264656A1 Memory Device Having Electrically Floating Body Transistor 有权
标题翻译：具有电浮体晶体管的存储器件
公开(公告)号：US20130264656A1
公开(公告)日：2013-10-10
申请号：US13746523
申请日：2013-01-22
申请人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
发明人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
IPC分类号： H01L29/78 , H01L29/70
CPC分类号： H01L27/10802 , G11C11/404 , G11C16/0433 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/1023 , H01L27/11524 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1095 , H01L29/36 , H01L29/70 , H01L29/73 , H01L29/7302 , H01L29/732 , H01L29/7841
摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
摘要翻译：半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。存储单元的第一区域与浮体区域电接触。存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。门位于第一和第二区之间。背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离第一和第二州。

5. 发明授权

US09208880B2 Content addressable memory device having electrically floating body transistor 有权
标题翻译：具有电浮体晶体管的内容可寻址存储器件
公开(公告)号：US09208880B2
公开(公告)日：2015-12-08
申请号：US14154138
申请日：2014-01-13
申请人： Benjamin S. Louie , Jin-Woo Han , Yuniarto Widjaja
发明人： Benjamin S. Louie , Jin-Woo Han , Yuniarto Widjaja
IPC分类号： G11C15/00 , G11C15/04 , G11C11/404 , G11C16/04
CPC分类号： G11C15/04 , G11C11/404 , G11C15/046 , G11C16/0458 , G11C16/0475 , G11C2211/4013 , G11C2211/4016 , H01L27/10802
摘要： A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
摘要翻译：内容可寻址存储单元包括第一浮体晶体管和第二浮体晶体管。第一浮体晶体管和第二浮体晶体管通过公共节点串联电连接。第一浮体晶体管和第二浮体晶体管存储互补数据。

6. 发明授权

US09029922B2 Memory device comprising electrically floating body transistor 有权
标题翻译：存储器件包括电浮体晶体管
公开(公告)号：US09029922B2
公开(公告)日：2015-05-12
申请号：US14203235
申请日：2014-03-10
申请人： Jin-Woo Han , Yuniarto Widjaja
发明人： Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L29/00 , H01L29/78 , H01L27/108 , G11C16/00
CPC分类号： H01L27/10802 , G11C11/404 , G11C11/407 , G11C16/00 , G11C16/0416 , H01L29/0649 , H01L29/7841
摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
摘要翻译：一种包括电浮体的半导体存储单元。提供了一种操作存储单元的方法。

7. 发明申请

US20140198551A1 Content Addressable Memory Device Having Electrically Floating Body Transistor 有权
标题翻译：具有电浮体晶体管的内容可寻址存储器件
公开(公告)号：US20140198551A1
公开(公告)日：2014-07-17
申请号：US14154138
申请日：2014-01-13
申请人： Benjamin S. Louie , Jin-Woo Han , Yuniarto Widjaja
发明人： Benjamin S. Louie , Jin-Woo Han , Yuniarto Widjaja
IPC分类号： G11C15/04
CPC分类号： G11C15/04 , G11C11/404 , G11C15/046 , G11C16/0458 , G11C16/0475 , G11C2211/4013 , G11C2211/4016 , H01L27/10802
摘要： A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
摘要翻译：内容可寻址存储单元包括第一浮体晶体管和第二浮体晶体管。第一浮体晶体管和第二浮体晶体管通过公共节点串联电连接。第一浮体晶体管和第二浮体晶体管存储互补数据。

8. 发明授权

US09230651B2 Memory device having electrically floating body transitor 有权
标题翻译：具有电浮体转换器的存储器件
公开(公告)号：US09230651B2
公开(公告)日：2016-01-05
申请号：US13746523
申请日：2013-01-22
申请人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
发明人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
IPC分类号： H01L29/78 , H01L29/70 , G11C16/04 , G11C11/404 , H01L27/108 , G11C16/10 , H01L27/115
CPC分类号： H01L27/10802 , G11C11/404 , G11C16/0433 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/1023 , H01L27/11524 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1095 , H01L29/36 , H01L29/70 , H01L29/73 , H01L29/7302 , H01L29/732 , H01L29/7841
摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
摘要翻译：半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。存储单元的第一区域与浮体区域电接触。存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。门位于第一和第二区之间。背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离第一和第二州。

9. 发明授权

US08923052B2 Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating 有权
标题翻译：具有易失性和多位，非易失性功能和操作方法的半导体存储器
公开(公告)号：US08923052B2
公开(公告)日：2014-12-30
申请号：US13196471
申请日：2011-08-02
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C11/34 , G11C14/00 , H01L27/105 , H01L27/108 , H01L29/78 , H01L27/115 , G11C16/04
CPC分类号： G11C14/0018 , G11C11/5671 , G11C14/00 , G11C16/02 , G11C16/0466 , G11C16/0475 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/115 , H01L29/7841 , H01L29/792
摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.
摘要翻译：描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器，以及位于捕获层上方的控制栅极。

10. 发明授权

US08547756B2 Semiconductor memory device having an electrically floating body transistor 失效
公开(公告)号：US08547756B2
公开(公告)日：2013-10-01
申请号：US12897516
申请日：2010-10-04
申请人： Yuniarto Widjaja , Zvi Or-Bach
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： G11C7/00
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

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