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1. 发明授权

US08159609B2 Image processing chip and related method for processing video 有权
标题翻译：图像处理芯片及其相关处理方法
公开(公告)号：US08159609B2
公开(公告)日：2012-04-17
申请号：US11685217
申请日：2007-03-13
申请人： Jin-Sheng Gong , Jui-Yuan Tsai , Yu-Pin Chou , Yueh-Hsing Huang
发明人： Jin-Sheng Gong , Jui-Yuan Tsai , Yu-Pin Chou , Yueh-Hsing Huang
IPC分类号： H04N7/00
CPC分类号： H04N5/08 , H04N5/185
摘要： The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.
摘要翻译：本发明涉及图像处理芯片及相关方法。图像处理芯片包括用于接收复合信号的引脚; 耦合到所述引脚的用于从所述复合信号中提取同步信号的同步信号检测电路; 耦合到所述引脚的钳位电路，用于根据所述同步信号调整所述复合信号的电压电平; 以及耦合到所述引脚的模数转换器，用于通过对所述复合信号进行采样来产生视频信号。

2. 发明申请

US20070211173A1 IMAGE PROCESSING CHIP AND RELATED METHOD THEREOF 有权
标题翻译：图像处理芯片及其相关方法
公开(公告)号：US20070211173A1
公开(公告)日：2007-09-13
申请号：US11685217
申请日：2007-03-13
申请人： Jin-Sheng Gong , Jui-Yuan Tsai , Yu-Pin Chou , Yueh-Hsing Huang
发明人： Jin-Sheng Gong , Jui-Yuan Tsai , Yu-Pin Chou , Yueh-Hsing Huang
IPC分类号： H03M1/12 , H04N5/16
CPC分类号： H04N5/08 , H04N5/185
摘要： The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.
摘要翻译：本发明涉及图像处理芯片及相关方法。图像处理芯片包括用于接收复合信号的引脚; 耦合到所述引脚的用于从所述复合信号中提取同步信号的同步信号检测电路; 耦合到所述引脚的钳位电路，用于根据所述同步信号调整所述复合信号的电压电平; 以及耦合到所述引脚的模数转换器，用于通过对所述复合信号进行采样来产生视频信号。

3. 发明授权

US07280091B2 Analog front-end circuit for digital displaying apparatus and control method thereof 有权
标题翻译：用于数字显示装置的模拟前端电路及其控制方法
公开(公告)号：US07280091B2
公开(公告)日：2007-10-09
申请号：US11279251
申请日：2006-04-11
申请人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
发明人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
IPC分类号： G09G3/36 , H03M1/06
CPC分类号： G09G5/04 , G09G3/2092
摘要： An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
摘要翻译：公开了一种数字显示器的模拟前端（AFE）电路，包括：第一电路，间歇地反转工作时钟以产生控制信号并产生采样信号，其中采样信号对应于工作时钟; 耦合到第一电路的第一模数转换器（ADC），用于根据采样信号将模拟视频信号转换成第一数字视频信号; 耦合到第一电路的第二模数转换器，用于根据采样信号将模拟视频信号转换成第二数字视频信号; 以及第一多路复用器，用于根据控制信号选择性地输出第一数字视频信号或第二数字视频信号。

4. 发明申请

US20060164551A1 ANALOG FRONT-END CIRCUIT FOR DIGITAL DISPLAYING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：用于数字显示设备的模拟前端电路及其控制方法
公开(公告)号：US20060164551A1
公开(公告)日：2006-07-27
申请号：US11279251
申请日：2006-04-11
申请人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
发明人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
IPC分类号： H03M1/12 , H04N5/14 , H04N5/05 , H04N9/455 , H04N9/64 , H04N5/45 , H04N9/44
CPC分类号： G09G5/04 , G09G3/2092
摘要： An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
摘要翻译：公开了一种数字显示器的模拟前端（AFE）电路，包括：第一电路，间歇地反转工作时钟以产生控制信号并产生采样信号，其中采样信号对应于工作时钟; 耦合到第一电路的第一模数转换器（ADC），用于根据采样信号将模拟视频信号转换成第一数字视频信号; 耦合到第一电路的第二模数转换器，用于根据采样信号将模拟视频信号转换成第二数字视频信号; 以及第一多路复用器，用于根据控制信号选择性地输出第一数字视频信号或第二数字视频信号。

5. 发明申请

US20080007656A1 Sync signal acquisition device 有权
标题翻译：同步信号采集装置
公开(公告)号：US20080007656A1
公开(公告)日：2008-01-10
申请号：US11822392
申请日：2007-07-05
申请人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
发明人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
IPC分类号： H04N5/06 , H04N9/72
CPC分类号： H04N5/08 , H04N5/185 , H04N9/44
摘要： A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
摘要翻译：公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

6. 发明申请

US20080032658A1 Analog front end device 审中-公开
标题翻译：模拟前端设备
公开(公告)号：US20080032658A1
公开(公告)日：2008-02-07
申请号：US11882039
申请日：2007-07-30
申请人： Jui-Yuan Tsai , Yu-Pin Chou
发明人： Jui-Yuan Tsai , Yu-Pin Chou
IPC分类号： H04B1/26
CPC分类号： H04N9/64
摘要： The invention discloses an analog front end device comprising a band-gap voltage reference circuit and at least one conversion circuit, wherein the conversion circuit includes a clamper, an input buffer, a low-pass filter, a high frequency gain unit and an analog to digital converter. The analog front end device utilize a high frequency gain unit to increase high frequency gain of the image analog signal for increasing the usable number of sampling phase of the image analog signal.
摘要翻译：本发明公开了一种包括带隙电压参考电路和至少一个转换电路的模拟前端装置，其中转换电路包括钳位器，输入缓冲器，低通滤波器，高频增益单元和模拟 - 数字转换器。模拟前端装置利用高频增益单元增加图像模拟信号的高频增益，以增加图像模拟信号的可用采样相位数。

7. 发明申请

US20080062185A1 FRAME SYNCHRONIZATION METHOD AND DEVICE UTILIZING FRAME BUFFER 有权
标题翻译：框架同步方法和使用框架缓冲器的设备
公开(公告)号：US20080062185A1
公开(公告)日：2008-03-13
申请号：US11531281
申请日：2006-09-13
申请人： Jin-Sheng Gong , Yu-Pin Chou , Hsu-Jung Tung
发明人： Jin-Sheng Gong , Yu-Pin Chou , Hsu-Jung Tung
IPC分类号： G09G5/36
CPC分类号： G09G5/37 , G06F3/14 , G09G5/12 , G09G2340/0435 , G09G2340/10
摘要： A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.
摘要翻译：帧同步方法包括：根据输入的时间序列临时存储帧缓冲器中的至少一个源帧的输入数据; 根据输入时间序列和延迟时间生成输出时间序列; 根据源帧的输入数据生成目的地帧的输出数据; 并根据输出时间序列输出目的地帧的输出数据; 其中所述源帧的平均帧速率与所述目的地帧的平均帧速率基本相同。

8. 发明授权

US08212938B2 Sync signal acquisition device 有权
标题翻译：同步信号采集装置
公开(公告)号：US08212938B2
公开(公告)日：2012-07-03
申请号：US11822392
申请日：2007-07-05
申请人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
发明人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
IPC分类号： H04N9/72
CPC分类号： H04N5/08 , H04N5/185 , H04N9/44
摘要： A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
摘要翻译：公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

9. 发明授权

US07830450B2 Frame synchronization method and device utilizing frame buffer 有权
标题翻译：帧同步方法和利用帧缓冲器的设备
公开(公告)号：US07830450B2
公开(公告)日：2010-11-09
申请号：US11531281
申请日：2006-09-13
申请人： Jin-Sheng Gong , Yu-Pin Chou , Hsu-Jung Tung
发明人： Jin-Sheng Gong , Yu-Pin Chou , Hsu-Jung Tung
IPC分类号： H04N7/01
CPC分类号： G09G5/37 , G06F3/14 , G09G5/12 , G09G2340/0435 , G09G2340/10
摘要： A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.
摘要翻译：帧同步方法包括：根据输入的时间序列临时存储帧缓冲器中的至少一个源帧的输入数据; 根据输入时间序列和延迟时间生成输出时间序列; 根据源帧的输入数据生成目的地帧的输出数据; 并根据输出时间序列输出目的地帧的输出数据; 其中所述源帧的平均帧速率与所述目的地帧的平均帧速率基本相同。

10. 发明申请

US20060197692A1 METHOD OF ADJUSTING SAMPLING CONDITION OF ANALOG TO DIGITAL CONVERTER AND APPARATUS THEREOF 有权
标题翻译：调制模拟数字转换器采样条件及其设备的方法
公开(公告)号：US20060197692A1
公开(公告)日：2006-09-07
申请号：US11306638
申请日：2006-01-05
申请人： Jin-Sheng Gong , Yu-Pin Kuo , Yu-Pin Chou , Hung-Jen Chu
发明人： Jin-Sheng Gong , Yu-Pin Kuo , Yu-Pin Chou , Hung-Jen Chu
IPC分类号： H03M1/12
CPC分类号： H03M1/1245
摘要： A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.
摘要翻译：一种调整采样条件以在模数转换器中产生采样时钟的方法包括对模拟输入信号执行模数转换，从而产生具有多个采样的数字采样信号; 计算数字采样信号中两个相邻采样之间的差值; 将差值与阈值进行比较; 如果所述差值大于所述阈值，则将所述差值加到差值的和中; 并根据差值的和生成模数转换器的采样时钟。

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