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1. 发明申请

US20050152202A1 Portable data storage apparatus 有权
标题翻译：便携式数据存储装置
公开(公告)号：US20050152202A1
公开(公告)日：2005-07-14
申请号：US10981367
申请日：2004-11-04
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G11C5/14 , G11C7/00 , G11C16/30
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card comprises a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.
摘要翻译：存储卡包括非易失性存储器和用于接收外部电源电压以向非易失性存储器提供工作电压的电源管理单元，其中当外部电源电压低于检测电压时，电源管理单元提升外部电源电压并将升压电压输出为非易失性存储器的工作电压。

2. 发明授权

US07706204B2 Portable data storage apparatus 有权
标题翻译：便携式数据存储装置
公开(公告)号：US07706204B2
公开(公告)日：2010-04-27
申请号：US12406654
申请日：2009-03-18
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.
摘要翻译：存储卡包括非易失性存储器; 以及电源管理单元，用于接收外部电源电压以向非易失性存储器提供工作电压。电源管理单元根据外部电源电压是否低于检测电压来提升/旁路外部电源电压，然后输出升压/旁路电压作为非易失性存储器的工作电压。

3. 发明授权

US07495989B2 Portable data storage apparatus 有权
标题翻译：便携式数据存储装置
公开(公告)号：US07495989B2
公开(公告)日：2009-02-24
申请号：US11484532
申请日：2006-07-11
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.
摘要翻译：存储卡包括非易失性存储器; 以及电源管理单元，用于接收外部电源电压以向非易失性存储器提供工作电压。电源管理单元根据外部电源电压是否低于检测电压来提升/旁路外部电源电压，然后输出升压/旁路电压作为非易失性存储器的工作电压。

4. 发明授权

US07518939B2 Portable data storage apparatus 有权
公开(公告)号：US07518939B2
公开(公告)日：2009-04-14
申请号：US11762537
申请日：2007-06-13
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

5. 发明申请

US20060249587A1 Portable data storage apparatus 有权
标题翻译：便携式数据存储装置
公开(公告)号：US20060249587A1
公开(公告)日：2006-11-09
申请号：US11484532
申请日：2006-07-11
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G06K19/06
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card comprises a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.
摘要翻译：存储卡包括非易失性存储器; 以及电源管理单元，用于接收外部电源电压以向非易失性存储器提供工作电压。电源管理单元根据外部电源电压是否低于检测电压来提升/旁路外部电源电压，然后输出升压/旁路电压作为非易失性存储器的工作电压。

6. 发明授权

US07092308B2 Portable data storage apparatus 有权
标题翻译：便携式数据存储装置
公开(公告)号：US07092308B2
公开(公告)日：2006-08-15
申请号：US10981367
申请日：2004-11-04
申请人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
发明人： Jin-Hyeok Choi , Sam-Yong Bahng , Chil-Hee Chung
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory card including a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.
摘要翻译：一种包括非易失性存储器的存储卡和用于接收外部电源电压以向非易失性存储器提供工作电压的电源管理单元，其中当外部电源电压低于检测电压时，电源管理单元提升外部电源电压并将升压电压输出为非易失性存储器的工作电压。

7. 发明申请

US20060231835A1 Semiconductor device including ROM interface pad 审中-公开
标题翻译：半导体器件包括ROM接口板
公开(公告)号：US20060231835A1
公开(公告)日：2006-10-19
申请号：US11398313
申请日：2006-04-05
申请人： Jin-Hyeok Choi , Sam-Yong Bahng
发明人： Jin-Hyeok Choi , Sam-Yong Bahng
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/48091 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01082 , H01L2924/3011 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality of via contacts formed in the inter-metal insulating layer, and a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.
摘要翻译：半导体器件包括形成在半导体衬底上的多层，多层包括第一电路图案，用于测试半导体器件的第二电路图案，形成在多层的预定区域上的第二电路，形成在多层的预定区域上的金属间绝缘层所述第二电路图案，形成在所述金属间绝缘层中的多个通孔接头以及设置在所述金属间绝缘层上的多个ROM接口焊盘，其中所述多个ROM接口焊盘与所述第二电路图形电连接通过多个通孔触点，并且彼此分离。

8. 发明申请

US20050202855A1 Circuit and method for preserving data in sleep mode of semiconductor device using test scan chain 有权
标题翻译：使用测试扫描链在半导体器件的睡眠模式下保存数据的电路和方法
公开(公告)号：US20050202855A1
公开(公告)日：2005-09-15
申请号：US11061903
申请日：2005-02-18
申请人： Jin-Hyeok Choi , Sam-Yong Bahng
发明人： Jin-Hyeok Choi , Sam-Yong Bahng
IPC分类号： G11C11/40 , H04B1/06 , H04B1/16 , H04B7/00
CPC分类号： G11C29/32
摘要： A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semiconductor device, and reduce power consumption in a standby state.
摘要翻译：数据存储电路和数据保存方法，用于在半导体器件使用测试扫描链处于睡眠模式时保存数据，其中数据存储电路包括睡眠模式控制单元和扫描链单元，睡眠模式控制响应于从外部接收的测试控制信号和睡眠模式控制信号中的一个输出扫描控制信号和扫描时钟信号，当接收到输出数据信号时，将输出数据信号存储在存储器中，并输出测试图形数据信号作为扫描数据信号，当接收到测试图形数据信号时，扫描链单元将存储在扫描链单元内的正常数据信号作为输出数据信号输出到睡眠模式控制单元，或者接收并输出根据扫描控制信号和扫描时钟信号将数据信号扫描到组合电路单元，数据存储电路和数据保存方法防止数据丢失为半通道模式，并且在待机状态下降低功耗。

9. 发明授权

US07376039B2 Circuit and method for preserving data in sleep mode of semiconductor device using test scan chain 有权
标题翻译：使用测试扫描链在半导体器件的睡眠模式下保存数据的电路和方法
公开(公告)号：US07376039B2
公开(公告)日：2008-05-20
申请号：US11061903
申请日：2005-02-18
申请人： Jin-Hyeok Choi , Sam-Yong Bahng
发明人： Jin-Hyeok Choi , Sam-Yong Bahng
IPC分类号： G11C5/14
CPC分类号： G11C29/32
摘要： A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semiconductor device, and reduce power consumption in a standby state.
摘要翻译：数据存储电路和数据保存方法，用于在半导体器件使用测试扫描链处于睡眠模式时保存数据，其中数据存储电路包括睡眠模式控制单元和扫描链单元，睡眠模式控制响应于从外部接收的测试控制信号和睡眠模式控制信号中的一个输出扫描控制信号和扫描时钟信号，当接收到输出数据信号时，将输出数据信号存储在存储器中，并输出测试图形数据信号作为扫描数据信号，当接收到测试图形数据信号时，扫描链单元将存储在扫描链单元内的正常数据信号作为输出数据信号输出到睡眠模式控制单元，或者接收并输出根据扫描控制信号和扫描时钟信号将数据信号扫描到组合电路单元，数据存储电路和数据保存方法防止数据丢失为半通道模式，并且在待机状态下降低功耗。

10. 发明授权

US08230303B2 Memory system and data processing method thereof 有权
标题翻译：存储系统及其数据处理方法
公开(公告)号：US08230303B2
公开(公告)日：2012-07-24
申请号：US12512097
申请日：2009-07-30
申请人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
发明人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2211/5646
摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.
摘要翻译：一种包括闪速存储器的存储器系统的数据处理方法，其包括判断从闪速存储器的选定页面开始读取的数据是否可校正。如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

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