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1. 发明授权

US07054201B2 Driving circuit for non-volatile DRAM 有权
标题翻译：用于非易失性DRAM的驱动电路
公开(公告)号：US07054201B2
公开(公告)日：2006-05-30
申请号：US10883151
申请日：2004-06-30
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Sang-Don Lee , Yil-Wook Kim , Young-Jun Park
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Sang-Don Lee , Yil-Wook Kim , Young-Jun Park
IPC分类号： G11C16/04
CPC分类号： G11C14/00 , G11C11/404 , G11C14/0018 , G11C16/30 , H01L27/105 , H01L27/115
摘要： A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.
摘要翻译：用于具有捕获电子或空穴的非导体的非易失性动态随机存取存储器（NVDRAM）中的驱动电路包括用于产生多个内部电源电压的内部电源电压发生器，每个具有至少两个不同的电压电平; 用于确定NVDRAM的操作模式的模式控制器; 电压电平选择器，用于响应于操作模式选择每个内部电源电压的一个电压电平，从而将每个内部电源电压的选定电压电平输出到行解码块和核心区域; 行解码块，用于接收内部电源电压并响应输入的地址输出内部电源电压; 以及具有多个单位单元的核心区域，每个单位单元存储数据，用于响应于所述多个内部电源电压的输入电压电平来访问数据。

2. 发明申请

US20060083068A1 Apparatus and method of driving non-volatile DRAM 失效
公开(公告)号：US20060083068A1
公开(公告)日：2006-04-20
申请号：US11284705
申请日：2005-11-21
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0416 , G11C11/406 , G11C11/40615 , G11C14/00
摘要： A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

3. 发明授权

US06996007B2 Apparatus and method of driving non-volatile DRAM 失效
标题翻译：驱动非易失性DRAM的装置和方法
公开(公告)号：US06996007B2
公开(公告)日：2006-02-07
申请号：US10749356
申请日：2003-12-31
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C11/406 , G11C11/40615 , G11C14/00
摘要： A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.
摘要翻译：包括在非易失性动态随机存取存储器（NVDRAM）中的单位单元包括耦合到字线的控制栅极层; 用于存储数据的电容器; 用于将电容器中的存储数据发送到位线的浮动晶体管，所述浮动晶体管的栅极是单层并用作临时数据存储器; 以及在所述控制栅极层和所述浮动晶体管的栅极之间的第一绝缘层，其中提供给所述浮动晶体管的主体的电压是可控的。

4. 发明申请

US20050047194A1 Non-volatile dynamic random access memory 有权
标题翻译：非易失性动态随机存取存储器
公开(公告)号：US20050047194A1
公开(公告)日：2005-03-03
申请号：US10749297
申请日：2003-12-31
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C16/04 , G11C11/24 , G11C11/404 , G11C14/00 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： G11C14/0018 , G11C11/404 , G11C16/0416
摘要： A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.
摘要翻译：一种用于操作具有多个存储单元的非易失性动态随机存取存储器（NVDRAM）器件的方法，具有电容器的每个单元和具有浮置栅极的晶体管包括以下步骤：（A）准备用于执行的上电模式 DRAM操作; 和（B）准备用于将存储的数据保存在存储单元中的断电模式。

5. 发明授权

US07224609B2 Apparatus and method of driving non-volatile DRAM 失效
标题翻译：驱动非易失性DRAM的装置和方法
公开(公告)号：US07224609B2
公开(公告)日：2007-05-29
申请号：US11284705
申请日：2005-11-21
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C16/30
CPC分类号： G11C16/0416 , G11C11/406 , G11C11/40615 , G11C14/00
摘要： A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.
摘要翻译：包括在非易失性动态随机存取存储器（NVDRAM）中的单位单元包括耦合到字线的控制栅极层; 用于存储数据的电容器; 用于将电容器中的存储数据发送到位线的浮动晶体管，所述浮动晶体管的栅极是单层并用作临时数据存储器; 以及在所述控制栅极层和所述浮动晶体管的栅极之间的第一绝缘层，其中提供给所述浮动晶体管的主体的电压是可控的。

6. 发明授权

US07099181B2 Non-volatile dynamic random access memory 有权
标题翻译：非易失性动态随机存取存储器
公开(公告)号：US07099181B2
公开(公告)日：2006-08-29
申请号：US10749297
申请日：2003-12-31
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C11/24
CPC分类号： G11C14/0018 , G11C11/404 , G11C16/0416
摘要： A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.
摘要翻译：一种用于操作具有多个存储单元的非易失性动态随机存取存储器（NVDRAM）器件的方法，具有电容器的每个单元和具有浮置栅极的晶体管包括以下步骤：（A）准备用于执行的上电模式 DRAM操作; 和（B）准备用于将存储的数据保存在存储单元中的断电模式。

7. 发明申请

US20050141316A1 Driving circuit for non-volatile DRAM 有权
标题翻译：用于非易失性DRAM的驱动电路
公开(公告)号：US20050141316A1
公开(公告)日：2005-06-30
申请号：US10883151
申请日：2004-06-30
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Sang-Don Lee , Yil-Wook Kim , Young-June Park
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Sang-Don Lee , Yil-Wook Kim , Young-June Park
IPC分类号： G11C16/04 , G11C7/00 , G11C11/404 , G11C11/407 , G11C14/00 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C14/00 , G11C11/404 , G11C14/0018 , G11C16/30 , H01L27/105 , H01L27/115
摘要： A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.
摘要翻译：用于具有捕获电子或空穴的非导体的非易失性动态随机存取存储器（NVDRAM）中的驱动电路包括用于产生多个内部电源电压的内部电源电压发生器，每个具有至少两个不同的电压电平; 用于确定NVDRAM的操作模式的模式控制器; 电压电平选择器，用于响应于操作模式选择每个内部电源电压的一个电压电平，从而将每个内部电源电压的选定电压电平输出到行解码块和核心区域; 行解码块，用于接收内部电源电压并响应输入的地址输出内部电源电压; 以及具有多个单位单元的核心区域，每个单位单元存储数据，用于响应于所述多个内部电源电压的输入电压电平来访问数据。

8. 发明申请

US20050041474A1 Apparatus and method of driving non-volatile dram 失效
标题翻译：驱动非挥发性剧本的装置和方法
公开(公告)号：US20050041474A1
公开(公告)日：2005-02-24
申请号：US10749356
申请日：2003-12-31
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Young-June Park , Sang-Don Lee , Yil-Wook Kim , Gi-Hyun Bae
IPC分类号： G11C14/00 , G11C16/04 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C11/34
CPC分类号： G11C16/0416 , G11C11/406 , G11C11/40615 , G11C14/00
摘要： A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.
摘要翻译：包括在非易失性动态随机存取存储器（NVDRAM）中的单位单元包括耦合到字线的控制栅极层; 用于存储数据的电容器; 用于将电容器中的存储数据发送到位线的浮动晶体管，所述浮动晶体管的栅极是单层并用作临时数据存储器; 以及在所述控制栅极层和所述浮动晶体管的栅极之间的第一绝缘层，其中提供给所述浮动晶体管的主体的电压是可控的。

9. 发明申请

US20050205939A1 Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same 审中-公开
标题翻译：具有能够俘获电荷的栅介电结构的易失性存储器件的晶体管及其制造方法
公开(公告)号：US20050205939A1
公开(公告)日：2005-09-22
申请号：US10883184
申请日：2004-06-30
申请人： Sang-Don Lee , Yil-Wook Kim , Jin-Hong Ahn , Young-June Park
发明人： Sang-Don Lee , Yil-Wook Kim , Jin-Hong Ahn , Young-June Park
IPC分类号： H01L27/10 , G11C11/401 , H01L21/265 , H01L21/28 , H01L21/314 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/792
CPC分类号： H01L21/26506 , H01L21/265 , H01L21/26513 , H01L21/28202 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/792
摘要： The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.
摘要翻译：本发明涉及具有能够俘获电荷的栅介电结构的易失性存储器件的晶体管及其制造方法。易失性存储器件的单元区域中的晶体管包括第一导电类型的衬底; 能够俘获电荷并形成在基板上的栅介质结构; 形成在栅介质结构上的栅极; 形成在栅极上的栅极绝缘层; 第二导电类型的源极/漏极，形成在设置在栅极的每个侧面下方的衬底的预定区域中; 以及第一导电类型的沟道离子注入区域，形成在设置在栅极下方的衬底的预定区域中。

10. 发明授权

US08115244B2 Transistor of volatile memory device with gate dielectric structure capable of trapping charges 有权
标题翻译：具有栅极电介质结构的易失性存储器件的晶体管能捕获电荷
公开(公告)号：US08115244B2
公开(公告)日：2012-02-14
申请号：US13094692
申请日：2011-04-26
申请人： Sang-Don Lee , Yil-Wook Kim , Jin-Hong Ahn , Young-June Park
发明人： Sang-Don Lee , Yil-Wook Kim , Jin-Hong Ahn , Young-June Park
IPC分类号： H01L29/76
CPC分类号： H01L21/265 , H01L21/26513 , H01L21/28202 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/792
摘要： The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.
摘要翻译：本发明涉及具有能够俘获电荷的栅介电结构的易失性存储器件的晶体管及其制造方法。易失性存储器件的单元区域中的晶体管包括第一导电类型的衬底; 能够俘获电荷并形成在基板上的栅介质结构; 形成在栅介质结构上的栅极; 形成在栅极上的栅极绝缘层; 第二导电类型的源极/漏极，形成在设置在栅极的每个侧面下方的衬底的预定区域中; 以及第一导电类型的沟道离子注入区域，形成在设置在栅极下方的衬底的预定区域中。

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