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1. 发明申请

US20120012969A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120012969A1
公开(公告)日：2012-01-19
申请号：US13240599
申请日：2011-09-22
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L27/108
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

2. 发明授权

US08030204B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08030204B2
公开(公告)日：2011-10-04
申请号：US12217932
申请日：2008-07-10
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

3. 发明申请

US20090035941A1 METHODS AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A PROCESSING CHAMBER 审中-公开
标题翻译：在加工室中制造半导体器件的方法和装置
公开(公告)号：US20090035941A1
公开(公告)日：2009-02-05
申请号：US12183421
申请日：2008-07-31
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Jun-Ho Park , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Jun-Ho Park , Ho-Ki Lee
IPC分类号： C23C16/00 , H01L21/44
CPC分类号： H01L21/28562 , C23C16/06 , C23C16/34 , C23C16/45519 , C23C16/54 , H01L21/6719 , H01L21/67207 , H01L21/76843 , H01L21/76846 , H01L21/76856
摘要： An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit.
摘要翻译：一种用于制造半导体器件的设备包括：处理室，被配置为在衬底上执行多个不同的处理。气体供应单元被配置为向处理室供应至少一种处理气体。至少一个上电极单元位于处理室的上部。至少一个下电极单元与上电极单元相对，并且构造成在其上支撑基板。驱动构件连接到下电极单元和上电极单元中的至少一个，并且被配置为移动下电极单元和/或上电极单元以控制上电极单元和下电极单元之间的距离。电源单元被配置为向所述上电极单元施加第一电力并且向所述下电极单元施加第二电力。

4. 发明申请

US20080136040A1 Methods of Forming Electrical Interconnects Using Non-Uniformly Nitrified Metal Layers and Interconnects Formed Thereby 审中-公开
标题翻译：使用非均匀硝化金属层和互连形成电互连的方法
公开(公告)号：US20080136040A1
公开(公告)日：2008-06-12
申请号：US11778344
申请日：2007-07-16
申请人： Jin-Ho Park , Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53266 , H01L21/76843 , H01L21/76856 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein. An electrically conductive pattern is formed in the opening. A second metal nitride layer is provided between the electrically conductive pattern and the nitrified first metal layer.
摘要翻译：形成电互连的方法包括：在半导体衬底上形成第一电绝缘层，然后在第一电绝缘层中形成开口。进行步骤以使开口的侧壁与其中具有不均匀氮浓度的硝化的第一金属层一起排列。在开口中形成导电图案。第二金属氮化物层设置在导电图案和硝化的第一金属层之间。

5. 发明授权

US08466556B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08466556B2
公开(公告)日：2013-06-18
申请号：US13240599
申请日：2011-09-22
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L29/40
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

6. 发明申请

US20090014879A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090014879A1
公开(公告)日：2009-01-15
申请号：US12217932
申请日：2008-07-10
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

7. 发明授权

US08294220B2 Method for forming silicide contacts 有权
标题翻译：形成硅化物接触的方法
公开(公告)号：US08294220B2
公开(公告)日：2012-10-23
申请号：US12685265
申请日：2010-01-11
申请人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
发明人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
IPC分类号： H01L23/50
CPC分类号： H01L21/76855 , H01L21/28556 , H01L21/76843
摘要： Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.
摘要翻译：可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。可以在衬底的第一器件区域上的介电层中形成第一接触孔。然后可以在第一接触孔中形成硅化物层。可以在形成第一接触孔和硅化物层之后形成第二接触孔。然后可以在第一和第二接触孔中执行第二硅化。

8. 发明申请

US20070105358A1 Method for forming silicide contacts 有权
标题翻译：形成硅化物接触的方法
公开(公告)号：US20070105358A1
公开(公告)日：2007-05-10
申请号：US11355112
申请日：2006-02-14
申请人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
发明人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76855 , H01L21/28556 , H01L21/76843
摘要： Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.
摘要翻译：可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。可以在衬底的第一器件区域上的介电层中形成第一接触孔。然后可以在第一接触孔中形成硅化物层。可以在形成第一接触孔和硅化物层之后形成第二接触孔。然后可以在第一和第二接触孔中执行第二硅化。

9. 发明授权

US07662716B2 Method for forming silicide contacts 有权
标题翻译：形成硅化物接触的方法
公开(公告)号：US07662716B2
公开(公告)日：2010-02-16
申请号：US11355112
申请日：2006-02-14
申请人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
发明人： Hyun-Su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
IPC分类号： H01L21/28 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76855 , H01L21/28556 , H01L21/76843
摘要： Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.
摘要翻译：可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。可以在衬底的第一器件区域上的介电层中形成第一接触孔。然后可以在第一接触孔中形成硅化物层。可以在形成第一接触孔和硅化物层之后形成第二接触孔。然后可以在第一和第二接触孔中执行第二硅化。

10. 发明申请

US20100109094A1 METHOD FOR FORMING SILICIDE CONTACTS 有权
标题翻译：形成硅胶接触的方法
公开(公告)号：US20100109094A1
公开(公告)日：2010-05-06
申请号：US12685265
申请日：2010-01-11
申请人： Hyun-su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
发明人： Hyun-su Kim , Kwang-Jin Moon , Sang-Woo Lee , Eun-Ok Lee , Ho-Ki Lee
IPC分类号： H01L23/50
CPC分类号： H01L21/76855 , H01L21/28556 , H01L21/76843
摘要： Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.
摘要翻译：可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。可以在衬底的第一器件区域上的介电层中形成第一接触孔。然后可以在第一接触孔中形成硅化物层。可以在形成第一接触孔和硅化物层之后形成第二接触孔。然后可以在第一和第二接触孔中执行第二硅化。

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