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1. 发明授权

US08836387B1 Methods and systems for reducing jitter 有权
标题翻译：减少抖动的方法和系统
公开(公告)号：US08836387B1
公开(公告)日：2014-09-16
申请号：US12984356
申请日：2011-01-04
申请人： Jin Xie , Bin Ni , Mats Oberg
发明人： Jin Xie , Bin Ni , Mats Oberg
IPC分类号： H03L7/06
CPC分类号： H03L7/093
摘要： Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.
摘要翻译：公开了用于补偿由锁相环产生的抖动的方法和系统。例如，在特定实施例中，用于减少抖动的锁相环装置可以包括被配置为产生VCO信号的电压控制振荡器（VCO）信号，相位检测电路被配置为将输入信号和VCO信号进行比较产生相位误差信号和摆率限制电路，其配置为接收相位误差信号，并对相位误差信号施加转换速率限制处理以产生修正的误差信号。

2. 发明申请

US20130047055A1 ERROR CORRECTION CODE TECHNIQUES FOR MATRICES WITH INTERLEAVED CODEWORDS 失效
标题翻译：错误校正代码技术用于具有互换代码的矩阵
公开(公告)号：US20130047055A1
公开(公告)日：2013-02-21
申请号：US13556466
申请日：2012-07-24
申请人： Mats Oberg , Jin Xie
发明人： Mats Oberg , Jin Xie
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11B20/1833 , G11B20/1866 , G11B2020/1846 , H03M13/2954
摘要： A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.
摘要翻译：解码系统包括解码器，第一模块和第二模块。解码器被配置为接收从光学存储介质读取的数据，并执行第一解码迭代和第二解码迭代以解码数据。第一解码迭代包括生成合成矩阵。第一模块被配置为基于所得到的矩阵中的多个字节的第一解码状态来确定接近反馈矩阵的失败字节的字节的第二解码状态。基于得到的矩阵生成反馈矩阵。第一模块被配置为基于第二解码状态将所选出的故障字节标记为擦除。第二模块被配置为校正在第二解码迭代期间标记为擦除的一个或多个字节。

3. 发明授权

US08031573B1 Supplementary timing recovery 有权
标题翻译：补充时间恢复
公开(公告)号：US08031573B1
公开(公告)日：2011-10-04
申请号：US12767393
申请日：2010-04-26
申请人： Jin Xie , Mats Oberg
发明人： Jin Xie , Mats Oberg
IPC分类号： G11B7/0045
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/1024 , G11B20/10444 , G11B20/10462 , G11B20/14 , G11B2220/2537
摘要： Aspects of the disclosure provide a signal processing circuit to reconstruct data from an analog signal. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a first timing compensation module, a phase-shift module and a second timing compensation module. The ADC receives an analog input signal, samples the analog input signal based on a sampling clock signal, and converts the sampled analog input signal into a digital output signal. The equalizer equalizes the digital output signal. The first timing compensation module detects a first timing error based on the digital output signal, and adjusts the sampling clock signal based on the first timing error. The phase-shift module phase-shifts the equalized digital output signal based on a phase-shift signal. The second timing compensation module detects a second timing error based on the equalized digital output signal, and adjusts the phase-shift signal based on the second timing error.
摘要翻译：本公开的方面提供了一种用于从模拟信号重构数据的信号处理电路。信号处理电路包括模数转换器（ADC），均衡器，第一定时补偿模块，相移模块和第二定时补偿模块。 ADC接收模拟输入信号，根据采样时钟信号采样模拟输入信号，并将采样的模拟输入信号转换为数字输出信号。均衡器使数字输出信号均衡。第一定时补偿模块基于数字输出信号检测第一定时误差，并且基于第一定时误差来调整采样时钟信号。相移模块基于相移信号对均衡的数字输出信号进行相移。第二定时补偿模块基于均衡的数字输出信号检测第二定时误差，并且基于第二定时误差来调整相移信号。

4. 发明授权

US07969848B1 System and method of decoupling asymmetry from baseline compensation 有权
标题翻译：将不对称与基线补偿分离的系统和方法
公开(公告)号：US07969848B1
公开(公告)日：2011-06-28
申请号：US12017786
申请日：2008-01-22
申请人： Jin Xie , Mats Oberg , Jingfeng Liu , Zachary Keirn
发明人： Jin Xie , Mats Oberg , Jingfeng Liu , Zachary Keirn
IPC分类号： G11B7/00
CPC分类号： G11B20/10324 , G11B7/00375 , G11B20/10009 , G11B20/10203 , G11B20/10351 , G11B2220/2537
摘要： A media defect compensation system and method may decouple effects of asymmetry from baseline error compensation computations. In some embodiments, a switching mechanism passes a baseline error signal into a baseline loop when a determination is made that a baseline error signal is not affected by asymmetry, and otherwise freezes the baseline loop when asymmetry may influence baseline error calculations.
摘要翻译：介质缺陷补偿系统和方法可以将非对称性的影响与基线误差补偿计算分离。在一些实施例中，当确定基线误差信号不受非对称性影响时，切换机构将基线误差信号传递到基线回路中，否则当不对称性可能影响基线误差计算时冻结基线回路。

5. 发明授权

US08358566B1 Method and device for detecting a sync mark 有权
标题翻译：用于检测同步标记的方法和装置
公开(公告)号：US08358566B1
公开(公告)日：2013-01-22
申请号：US12359855
申请日：2009-01-26
申请人： Mats Oberg , Jin Xie
发明人： Mats Oberg , Jin Xie
IPC分类号： G11B5/09
CPC分类号： G11B7/00736 , G11B20/10009
摘要： A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.
摘要翻译：一种用于确定频率误差以延长诸如光盘驱动器之类的存储装置的定时恢复电路的拉入范围的方法和装置。检测与存储装置的存储格式相关联的代码，并且确定代码的出现之间的距离。将计算出的距离与预期距离进行比较以确定差异。根据差异，确定频率误差。

6. 发明授权

US08812941B2 Viterbi device and method using a posteriori information 有权
标题翻译：维特比设备和使用后验信息的方法
公开(公告)号：US08812941B2
公开(公告)日：2014-08-19
申请号：US13536041
申请日：2012-06-28
申请人： Jin Xie , Mats Oberg
发明人： Jin Xie , Mats Oberg
IPC分类号： H03M13/03
CPC分类号： H04L1/0054 , H04L1/0047
摘要： New and useful methods and systems for providing improved performance of a Viterbi device are disclosed. For example, in an embodiment a Viterbi device includes metric circuitry configured to determine branch metrics using at least one of a variance signal based on both received data and detected data of the Viterbi device and a priori probabilities of available state transitions within a trellis of the Viterbi device.
摘要翻译：公开了用于提供维特比设备的改进性能的新的有用的方法和系统。例如，在一个实施例中，维特比设备包括度量电路，其被配置为使用基于接收数据和维特比设备的检测数据的方差信号中的至少一个来确定分支度量，以及在所述维特比设备的网格内的可用状态转换的先验概率维特比设备。

7. 发明授权

US08675461B1 Adjusting a defect threshold 失效
标题翻译：调整缺陷阈值
公开(公告)号：US08675461B1
公开(公告)日：2014-03-18
申请号：US12546225
申请日：2009-08-24
申请人： Jin Xie , Mats Oberg
发明人： Jin Xie , Mats Oberg
IPC分类号： G11B7/00 , G11B20/18 , G11B27/36
CPC分类号： G06F11/073 , G11B20/10314 , G11B20/18 , G11B20/1816 , G11B2220/2537
摘要： Devices, methods, and other embodiments associated with adjusting a defect threshold are described. In one embodiment, an apparatus includes defect detection logic and threshold adjustment logic. The defect detection logic determines, by using a defect threshold, if a read channel has read data from a defective portion of an optical disc. The threshold adjustment logic adjusts the defect threshold based, at least in part, on a gain value of a gain loop associated with the read channel.
摘要翻译：描述了与调整缺陷阈值相关联的设备，方法和其他实施例。在一个实施例中，装置包括缺陷检测逻辑和阈值调整逻辑。缺陷检测逻辑通过使用缺陷阈值来确定读取通道是否具有从光盘的缺陷部分读取数据。至少部分地基于与读取通道相关联的增益循环的增益值来调整缺陷阈值。

8. 发明授权

US08671328B2 Error correction code techniques for matrices with interleaved codewords 失效
标题翻译：具有交错码字的矩阵的纠错码技术
公开(公告)号：US08671328B2
公开(公告)日：2014-03-11
申请号：US13556466
申请日：2012-07-24
申请人： Mats Oberg , Jin Xie
发明人： Mats Oberg , Jin Xie
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B20/1866 , G11B2020/1846 , H03M13/2954
摘要： A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.
摘要翻译：解码系统包括解码器，第一模块和第二模块。解码器被配置为接收从光学存储介质读取的数据，并执行第一解码迭代和第二解码迭代以解码数据。第一解码迭代包括生成合成矩阵。第一模块被配置为基于所得到的矩阵中的多个字节的第一解码状态来确定接近反馈矩阵的失败字节的字节的第二解码状态。基于得到的矩阵生成反馈矩阵。第一模块被配置为基于第二解码状态将所选出的故障字节标记为擦除。第二模块被配置为校正在第二解码迭代期间标记为擦除的一个或多个字节。

9. 发明授权

US08660171B1 Method and apparatus for timing jitter measurement 失效
标题翻译：定时抖动测量的方法和装置
公开(公告)号：US08660171B1
公开(公告)日：2014-02-25
申请号：US12192877
申请日：2008-08-15
申请人： Mats Oberg , Jin Xie , Bin Ni
发明人： Mats Oberg , Jin Xie , Bin Ni
IPC分类号： H04B17/00
CPC分类号： H04L1/205 , G01R31/31709 , H04B17/364
摘要： A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.
摘要翻译：用于测量数字域中的定时抖动的定时抖动测量电路可以使用内插器组对来自媒体读取器的信号进行过采样，零交叉估计器估计内插器组的输出中的零交叉时刻和时间间隔分析器（TIA）来计算定时抖动，作为估计的过零点与时钟信号中的预期过零点的偏差。定时抖动测量电路可以集成到数字电路中，因为它避免使用模拟设备。因此，它可以简化芯片设计，降低功耗并节省空间。

10. 发明授权

US08634285B1 Timing loop with large pull-in range 失效
标题翻译：定时回路具有大的拉入范围
公开(公告)号：US08634285B1
公开(公告)日：2014-01-21
申请号：US13603795
申请日：2012-09-05
申请人： Mats Oberg , Jin Xie
发明人： Mats Oberg , Jin Xie
IPC分类号： G11B7/00
CPC分类号： G11B20/10222 , G11B20/10435
摘要： Aspects of the disclosure provide a sync mark detector. The sync mark detector includes a first unit configured to decay over time a value indicating a length of a bit format, a second unit configured to compare the decayed value with a detected length of the bit format to determine a new length, and a third unit configured to detect a sync mark based on the detected length and the new length.
摘要翻译：本公开的方面提供了同步标记检测器。同步标记检测器包括被配置为随时间衰减指示位格式的长度的值的第一单元，被配置为将衰减值与所检测的位格式的长度进行比较以确定新长度的第二单元，以及第三单元被配置为基于检测到的长度和新的长度来检测同步标记。

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