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1. 发明授权

US5208914A Method and apparatus for non-sequential resource access 失效
标题翻译：用于非顺序资源访问的方法和装置
公开(公告)号：US5208914A
公开(公告)日：1993-05-04
申请号：US535786
申请日：1990-06-11
申请人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
发明人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/00 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.
摘要翻译：用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。请求信号验证地址和请求标签。该地址指定所请求的数据在内存中的位置。请求标签指定在将数据返回到处理器时放置数据的位置。用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到请求者。与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑。

2. 发明授权

US5165038A Global registers for a multiprocessor system 失效
标题翻译：多处理器系统的全局寄存器
公开(公告)号：US5165038A
公开(公告)日：1992-11-17
申请号：US536198
申请日：1990-06-11
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F15/16 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.
摘要翻译：用于多处理器系统的全局寄存器支持多个并行访问路径，用于在单独的全局寄存器集合上同时操作，每组全局寄存器被称为全局寄存器文件。与全局寄存器相关联的仲裁机制用于解析对单个全局寄存器文件的多个同时请求。算术和逻辑单元（ALU）也与每个全局寄存器文件相关联，以允许对该全局寄存器文件中的任何全局寄存器的整个寄存器值执行原子算术运算。

3. 发明授权

US5524255A Method and apparatus for accessing global registers in a multiprocessor system 失效
标题翻译：用于在多处理器系统中访问全局寄存器的方法和装置
公开(公告)号：US5524255A
公开(公告)日：1996-06-04
申请号：US379123
申请日：1995-01-27
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80 , G06F15/163
CPC分类号： G06F9/3004 , G06F15/17 , G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30043 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.
摘要翻译：全局注册系统提供在多处理器系统中共享公共存储器的多个处理器之间的通信和协调，多处理器系统访问共享资源电路内的一个或多个与公共存储器分离的寄存器，并且可由多个处理器对称地访问多处理器系统全局寄存器系统由处理器从先前分配的间接地址确定的直接地址和访问存储在全局寄存器中的数据的指令访问。存储在所选择的一个寄存器中的数据值的算术或逻辑运算由独立于处理器或公共存储器的全局寄存器系统执行，以便修改所选择的全局寄存器中的数据值，作为执行的原子操作的一部分响应于从一个处理器接收的单个读取和修改指令。

4. 发明授权

US5499356A Method and apparatus for a multiprocessor resource lockout instruction 失效
标题翻译：多处理器资源锁定指令的方法和装置
公开(公告)号：US5499356A
公开(公告)日：1996-03-12
申请号：US173923
申请日：1993-12-28
申请人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
发明人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F12/14
CPC分类号： G06F15/8076 , G06F15/17381 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30069 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/526 , G06F2209/521
摘要： A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.
摘要翻译：一种用于在共享存储器中提供资源锁定机制的方法和装置，该多处理器系统能够在同一存储器操作期间同时执行读取和写入操作。本发明的加载和标志指令可以在相同的存储器操作期间执行读取操作，随后将预选标志值写入同一个存储器位置。加载和标志指令特别适用于在蒙特卡罗应用程序中使用的资源锁定机制。

5. 发明授权

US5381536A Method and apparatus for separate mark and wait instructions for processors having multiple memory ports 失效
标题翻译：用于具有多个存储器端口的处理器的单独标记和等待指令的方法和装置
公开(公告)号：US5381536A
公开(公告)日：1995-01-10
申请号：US249084
申请日：1994-05-25
申请人： Andrew E. Phelps , Roger E. Eckert , Richard E. Hessel
发明人： Andrew E. Phelps , Roger E. Eckert , Richard E. Hessel
IPC分类号： G06F9/38 , G06F11/36 , G06F12/00 , G06F13/00 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834
摘要： The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.
摘要翻译：本发明提供一种用于处理具有多个存储器端口的处理器中的存储器危险的方法和装置，其中可能与存储器危险有关的存储器请求的标记操作与等待存储器危险清除的操作分离。将记忆危害的标记操作与等待记忆危害的操作分开清除允许编译器在时间间隔内调度其他指令以及其他指令，而不是指向存储器危险序列中涉及的存储器位置的其他存储器操作在标记操作和等待记忆危害之间清除。等待期结束，一旦清楚的是，标记的内存请求将按照发出的顺序执行。

6. 发明授权

US06195676B1 Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes 失效
标题翻译：用于实现进程分配调度的多处理器操作系统程序中用户端调度的方法和装置
公开(公告)号：US06195676B1
公开(公告)日：2001-02-27
申请号：US08003000
申请日：1993-01-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F946
CPC分类号： G06F9/30149 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

7. 发明授权

US5179702A System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling 失效
标题翻译：用于使用基于无政府状态的调度器来控制并行执行线程调度的高度并行多处理器的系统和方法
公开(公告)号：US5179702A
公开(公告)日：1993-01-12
申请号：US537466
申请日：1990-06-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F9/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F9/48 , G06F11/28 , G06F11/36 , G06F12/02 , G06F12/08 , G06F12/12 , G06F15/16 , G06F15/167 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F9/30149 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

8. 发明授权

US07808503B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07808503B2
公开(公告)日：2010-10-05
申请号：US11613093
申请日：2006-12-19
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/00 , G06T15/10
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

9. 发明授权

US06717576B1 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US06717576B1
公开(公告)日：2004-04-06
申请号：US09377503
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

10. 发明授权

US06614444B1 Apparatus and method for fragment operations in a 3D-graphics pipeline 有权
标题翻译： 3D图形管道中的碎片操作的装置和方法
公开(公告)号：US06614444B1
公开(公告)日：2003-09-02
申请号：US09372137
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Sushma S. Trivedi , Sam Ng , Lindy Fung , Richard E. Hessel , Jack Benkual
发明人： Jerome F. Duluk, Jr. , Sushma S. Trivedi , Sam Ng , Lindy Fung , Richard E. Hessel , Jack Benkual
IPC分类号： G09G500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a stage for performing a fragment operation on a fragment on a per-pixel basis, as well as a stage for performing a fragment operation on the fragment on a per-sample basis. The stage for performing on a per-pixel basis is one of the following: a scissor-test stage, a stipple-test stage, an alpha-test stage or a colorest stage, and the stage for performing on a per-sample basis is one of the following: a Z-test stage, a blending stage or a dithering stage. The apparatus programmatically selects whether to perform a stencil test on a per-pixel or a per-sample basis and performs the stencil test on the selected basis. The apparatus also programmatically selects pixel samples for per-sample operations, where the sample selections differ with different instances of the same per-sample operation. The apparatus also programmatically selects a set of subdivisions of a pixel as samples for use in the per-sample fragment operation, programmatically assigns different weights to at least two samples in the set and performs the per-sample fragments operation on the fragment using the programmatically selected and differently weighted samples.
摘要翻译：用于渲染3D图形图像的装置和方法。该装置包括用于从图形应用程序接收命令的端口，用于将呈现的图像发送到显示器的输出端和耦合到端口和输出端的分段操作流水线，流水线包括用于执行片段操作的级基于每个像素的片段，以及在每个样本的基础上对片段执行片段操作的阶段。基于每像素执行的阶段是以下之一：剪刀测试阶段，点测试阶段，α测试阶段或阶段阶段，以及每个采样基础执行的阶段是以下之一：Z测试阶段，混合阶段或抖动阶段。该设备以编程方式选择是在每个像素还是每个样本的基础上执行模板测试，并在所选择的基础上执行模板测试。该设备还以编程方式选择每采样操作的像素采样，其中样本选择与相同每采样操作的不同实例不同。该装置还以编程方式选择一组像素的细分作为在每个样本片段操作中使用的样本，以编程方式向集合中的至少两个样本分配不同的权重，并使用编程方式对该片段执行每个样本片段的操作选择和不同加权的样本。

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