专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050154838A1 Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected 有权
标题翻译：当检测到虚拟高速缓存行共享时，用于将高速缓存条目自动移动到专用存储器的方法和装置
公开(公告)号：US20050154838A1
公开(公告)日：2005-07-14
申请号：US10757227
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/318 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/3836 , G06F9/30181 , G06F9/384 , G06F9/3857 , G06F12/0806 , G06F12/0815
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory. Thus, when the code again attempts to access this area of the cache, the access is redirected to the new cache or memory area rather than to the previous area of the cache that was subject to false sharing. In this way, reloads of the cache line may be avoided.
摘要翻译：提供了用于处理指令的数据处理系统中的方法，装置和计算机指令。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在一些实施例中，当使用性能指示符和计数器确定高速缓存行被错误地共享时，可以产生中断并将其发送到性能监视应用。性能监视应用程序的中断处理程序将会将此中断视为指示高速缓存行的虚假共享。不是以正常方式重新加载高速缓存线，正在访问的数据或指令可以写入专用于虚拟高速缓存行共享数据的高速缓存或存储器区域的单独区域。然后可以通过将指针插入到高速缓存或存储器的这个新区域来修改代码。因此，当代码再次尝试访问高速缓存的这个区域时，访问被重定向到新的高速缓存或存储器区域，而不是高速缓存的先前区域被错误共享。以这种方式，可以避免高速缓存线的重新加载。

2. 发明申请

US20050071822A1 Method and apparatus for counting instruction and memory location ranges 失效
标题翻译：用于计数指令和存储器位置范围的方法和装置
公开(公告)号：US20050071822A1
公开(公告)日：2005-03-31
申请号：US10675872
申请日：2003-09-30
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3466 , G06F2201/81 , G06F2201/88
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is identified if the instruction is within the contiguous range of instructions. With memory location accesses, an access to a memory location is identified. A determination of whether the memory location is within a contiguous range of memory locations is made. Access information is identified if the memory location is within the contiguous range of memory locations.
摘要翻译：数据处理系统中的方法，装置和计算机指令，用于处理指令并监视对存储器位置范围的访问。确定执行指令。确定指令是否在连续的指令范围内。如果指令在指令的相邻范围内，则识别与指令相关的执行信息。利用存储器位置访问，识别对存储器位置的访问。确定存储器位置是否在存储器位置的连续范围内。如果存储器位置在存储器位置的连续范围内，则识别访问信息。

3. 发明申请

US20050154839A1 Method and apparatus for identifying false cache line sharing 有权
标题翻译：识别虚拟高速缓存行共享的方法和装置
公开(公告)号：US20050154839A1
公开(公告)日：2005-07-14
申请号：US10757249
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0806 , G06F12/0815
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators may be utilized to obtain information regarding the nature of the cache hits and reloads of cache lines within the instruction or data cache. These embodiments may be used to determine whether processors of a multiprocessor system, such as a symmetric multiprocessor (SMP) system, are truly sharing a cache line or if there is false sharing of a cache line. This determination may then be used as a means for determining how to better store the instructions/data of the cache line to prevent false sharing of the cache line.
摘要翻译：提供了用于处理指令的数据处理系统中的方法，装置和计算机指令。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在一些实施例中，性能指示符可用于获得关于高速缓存命中的性质和指令或数据高速缓存内的高速缓存行的重新加载的信息。这些实施例可以用于确定诸如对称多处理器（SMP）系统的多处理器系统的处理器是真正共享高速缓存行还是存在高速缓存行的虚假共享。然后可以将该确定用作确定如何更好地存储高速缓存行的指令/数据以防止高速缓存行的虚假共享的手段。

4. 发明申请

US20050102673A1 Apparatus and method for autonomic hardware assisted thread stack tracking 失效
标题翻译：自动硬件辅助线程堆栈跟踪的装置和方法
公开(公告)号：US20050102673A1
公开(公告)日：2005-05-12
申请号：US10703658
申请日：2003-11-06
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/06 , G06F9/44 , G06F9/46
CPC分类号： G06F11/3636
摘要： A method and apparatus for providing an autonomic mechanism for tracking thread stacks during a trace of a computer program. The method and apparatus include hardware assistance mechanisms that allow the processor to autonomically maintain a work area for each thread where a call stack is stored. With the apparatus and method, the operating system of the computing device informs the operating system of the size of the data area to allocate to a particular thread work area. In addition, when a trace of a computer program is to be performed, the trace software, via the operating system, informs the processor to begin maintaining the thread call stack information in the thread work area. For each thread in the computer program execution, the processor maintains a work area having a size that is determined based on the size communicated by the operating system. The work area is designated by address and length information stored in control registers of the processor. The processor contains microcode that is used to cause the processor to automatically store thread tracking information in the work areas designated by the control registers of the processor when the control bit is set.
摘要翻译：一种在计算机程序的跟踪期间提供用于跟踪线程栈的自主机制的方法和装置。该方法和装置包括硬件辅助机制，其允许处理器自动维护存储调用堆栈的每个线程的工作区域。利用该装置和方法，计算装置的操作系统向操作系统通知要分配给特定线程工作区的数据区的大小。此外，当要执行跟踪计算机程序时，经由操作系统的跟踪软件通知处理器开始在线程工作区域中维护线程调用堆栈信息。对于计算机程序执行中的每个线程，处理器维护具有基于由操作系统传送的大小确定的大小的工作区域。工作区域由存储在处理器的控制寄存器中的地址和长度信息指定。处理器包含微码，用于使处理器在设置控制位时，将线程跟踪信息自动存储在由处理器的控制寄存器指定的工作区域中。

5. 发明申请

US20050071610A1 Method and apparatus for debug support for individual instructions and memory locations 审中-公开
标题翻译：用于调试的方法和装置支持各个指令和存储单元
公开(公告)号：US20050071610A1
公开(公告)日：2005-03-31
申请号：US10675751
申请日：2003-09-30
申请人： Jimmie DeWitt , Frank Levine , Enio Pineda , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Enio Pineda , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/00 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： A method, apparatus, and computer instructions in a data processing system for monitoring processing of instructions and memory locations. An instruction is received in the data processing system for execution. If an enabled state is present, a determination is made whether the instruction is associated with an indicator in a shadow memory. A selected action is performed in response to the indicator being associated with the instruction. Responsive to being in an enabled state when a data access to a memory location occurs, a determination is made as to whether the memory location is associated with an indicator in a shadow memory. A selected action is performed in response to the indicator being associated with the memory location.
摘要翻译：数据处理系统中的方法，装置和计算机指令，用于监视指令和存储器位置的处理。在数据处理系统中接收指令执行。如果存在启用状态，则确定指令是否与影子存储器中的指示符相关联。响应于与指令相关联的指示符执行所选择的动作。响应于在存储器位置的数据访问发生时处于使能状态，确定存储器位置是否与影子存储器中的指示符相关联。响应于与存储器位置相关联的指示符执行所选择的动作。

6. 发明申请

US20050210454A1 Method and apparatus for determining computer program flows autonomically using hardware assisted thread stack tracking and cataloged symbolic data 失效
标题翻译：使用硬件辅助线程堆栈跟踪和编目的符号数据自动地确定计算机程序流的方法和装置
公开(公告)号：US20050210454A1
公开(公告)日：2005-09-22
申请号：US10803663
申请日：2004-03-18
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/44
CPC分类号： G06F11/3409 , G06F11/3471 , G06F2201/86 , G06F2201/88
摘要： A method, apparatus, and computer instructions for determining computer flows autonomically using hardware assisted thread stack and cataloged symbolic data. When a new thread is spawned during execution of a computer program, new thread work area is allocated by the operating system in memory for storage of call stack information for the new thread. Hardware registers are set with values corresponding to the new thread work area. Upon context switch, values of the registers are saved in a context save area for future restoration. When call stack data is post-processed, the operating system or a device driver copies call stack data from the thread work areas to a consolidated buffer and each thread is mapped to a process. Symbolic data may be obtained based on the process identifier and address of the method/routine that was called/returned in the thread. Corresponding program flow is determined using retrieved symbolic data and call stack data.
摘要翻译：一种用于使用硬件辅助线程堆栈和编目的符号数据自主地确定计算机流的方法，装置和计算机指令。当在执行计算机程序期间产生新的线程时，操作系统将新的线程工作区分配给存储器，以存储新线程的调用堆栈信息。硬件寄存器设置为与新线程工作区域对应的值。在上下文切换时，寄存器的值保存在上下文保存区域中，以备将来恢复。当调用堆栈数据进行后处理时，操作系统或设备驱动程序将调用堆栈数据从线程工作区域复制到统一缓冲区，并将每个线程映射到进程。可以基于在线程中调用/返回的方法/例程的进程标识符和地址获得符号数据。使用检索到的符号数据和调用堆栈数据确定相应的程序流程。

7. 发明申请

US20050155022A1 Method and apparatus for counting instruction execution and data accesses to identify hot spots 审中-公开
标题翻译：用于计数指令执行和数据访问以识别热点的方法和装置
公开(公告)号：US20050155022A1
公开(公告)日：2005-07-14
申请号：US10757248
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F7/38
CPC分类号： G06F11/3612
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments of the present invention, the counts associated with the performance indicators may be checked to determine if the counts are above a threshold. If a count is above a threshold, the associated instruction/data address may be identified as a “hot spot” and optimization of the execution of the code may be performed based on the identification of the hot spot.
摘要翻译：提供了用于处理指令的数据处理系统中的方法，装置和计算机指令。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在本发明的一些实施例中，可以检查与性能指标相关联的计数以确定计数是否高于阈值。如果计数高于阈值，则相关联的指令/数据地址可以被识别为“热点”，并且可以基于热点的识别来执行代码的执行的优化。

8. 发明申请

US20050155020A1 Method and apparatus for autonomic detection of cache "chase tail" conditions and storage of instructions/data in "chase tail" data structure 失效
标题翻译：用于自动检测缓存“追尾”条件的方法和装置以及“追尾”数据结构中指令/数据的存储
公开(公告)号：US20050155020A1
公开(公告)日：2005-07-14
申请号：US10757256
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F7/38 , G06F12/12
CPC分类号： G06F12/126
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. there is a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.
摘要翻译：提供了用于处理指令的数据处理系统中的方法，装置和计算机指令。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。性能指标和计数器值可以用作识别高速缓存命中和高速缓存未命中的机制。每次执行关注程序的指令并且每次必须将指令重新加载到高速缓存中时，性能计数器都会递增。从这些计数器的值可以确定高速缓存命中错失率。当高速缓存命中错失率变得小于预定阈值时，即存在比高速缓存命中更多数量的高速缓存未命中，本发明可以确定已经出现了问题状况并启动“追尾”操作，以避免重写条目在缓存中。

9. 发明申请

US20050155018A1 Method and apparatus for generating interrupts based on arithmetic combinations of performance counter values 审中-公开
标题翻译：基于性能计数器值的算术组合产生中断的方法和装置
公开(公告)号：US20050155018A1
公开(公告)日：2005-07-14
申请号：US10757212
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments of the present invention, arithmetic combinations of counter values generated based on the encountering of performance indicators may be generated and compared to threshold values to determine whether to generate interrupts to the monitoring application. In such embodiments, the microcode of the processor is programmed to check the counter values of counters specified by the monitoring application, combine the counter values in a manner specified by the monitoring application, and then compare the combined value to a threshold value supplied by the performance monitoring application. In this way, more complex conditioning of interrupts may be provided within the hardware of the processor.
摘要翻译：提供了用于处理指令的数据处理系统中的方法，装置和计算机指令。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在本发明的一些实施例中，可以生成基于遇到性能指示符而产生的计数器值的算术组合，并将其与阈值进行比较，以确定是否产生到监视应用程序的中断。在这样的实施例中，处理器的微码被编程为检查由监视应用指定的计数器的计数器值，以监视应用指定的方式组合计数器值，然后将组合值与由性能监控应用。以这种方式，可以在处理器的硬件内提供更复杂的中断调节。

10. 发明申请

US20050154812A1 Method and apparatus for providing pre and post handlers for recording events 有权
标题翻译：用于提供记录事件的前处理程序和后处理程序的方法和装置
公开(公告)号：US20050154812A1
公开(公告)日：2005-07-14
申请号：US10757192
申请日：2004-01-14
申请人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
发明人： Jimmie DeWitt , Frank Levine , Christopher Richardson , Robert Urquhart
IPC分类号： G06F9/38 , G06F9/46 , G06F13/24
CPC分类号： G06F13/24
摘要： A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.
摘要翻译：一种方法，装置和计算机指令，用于在进入或退出中断处理程序之后提供前处理程序和后处理程序来记录跟踪记录。跟踪记录包括发生中断的“从”地址或执行分支指令的位置，或者分支的“到”地址到所选择的性能监视事件的大小写和计数。时间戳可能与每个事件相关联。在一个实施例中，前处理程序和后处理程序与分支上的陷阱一起使用，以在分支之前和之后记录跟踪记录。在另一个实施例中，预处理程序能够记录在执行中断服务程序之前发生的跟踪记录。启用后台处理程序来记录在执行中断服务程序之后并在返回到正常执行之前发生的跟踪记录。所得到的低级别性能跟踪数据可以由用户以后收集以进行更结构化的性能分析。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式