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1. 发明申请

US20190207288A1 CIRCUITS FOR WIRELESS COMMUNICATION ON MULTIPLE FREQUENCY BANDS 审中-公开
公开(公告)号：US20190207288A1
公开(公告)日：2019-07-04
申请号：US16303246
申请日：2017-05-22
申请人： Jianxun ZHU , Peter R. KINGET
发明人： Jianxun ZHU , Peter R. KINGET
IPC分类号： H01P5/18 , H01P5/22 , H01Q21/28 , H04B1/04 , H04B1/18 , H04B1/44 , H04B1/525 , H04L5/14 , H04L5/00
CPC分类号： H01P5/18 , H01P5/227 , H01Q21/28 , H04B1/00 , H04B1/0458 , H04B1/18 , H04B1/44 , H04B1/52 , H04B1/525 , H04L5/001 , H04L5/0023 , H04L5/143
摘要： Circuits for wireless communication on multiple frequency bands are provided. In accordance with some embodiments, transceivers are provided, the transceivers comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; an antenna coupled to the first in port; a first transmitter having an output coupled to the first cpl port; and a first receiver having an input coupled to the first cpl port.

2. 发明申请

US20100019300A1 MULTILAYER INTEGRATED CIRCUIT HAVING AN INDUCTOR IN STACKED ARRANGEMENT WITH A DISTRIBUTED CAPACITOR 审中-公开
标题翻译：具有分布式电容器的堆叠布置中的电感器的多层集成电路
公开(公告)号：US20100019300A1
公开(公告)日：2010-01-28
申请号：US12491608
申请日：2009-06-25
申请人： Shih-An YU , Peter R. KINGET
发明人： Shih-An YU , Peter R. KINGET
IPC分类号： H01L29/94
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/0617 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments provide a multilayer integrated circuit, including: a semiconductor substrate including a plurality of channels extending into the substrate from a surface of the substrate; a distributed capacitor including a plurality of gates formed on the surface of the substrate over the channels, and further including an insulator between the gates and the channels, the gates being spaced apart along the surface of the substrate; an interconnect layer formed over the distributed capacitor, the interconnect layer including a plurality of conductors, at least a first conductor being connected to at least some of the gates and at least a second conductor being connected to at least some of the channels; and an inductor formed over the interconnect layer, the inductor including at least conductor arranged on a layer.
摘要翻译：一些实施例提供了一种多层集成电路，包括：半导体衬底，其包括从衬底的表面延伸到衬底中的多个沟道; 分布式电容器，包括在通道上形成在基板的表面上的多个栅极，并且还包括在栅极和沟道之间的绝缘体，栅极沿着衬底的表面间隔开; 形成在所述分布式电容器上的互连层，所述互连层包括多个导体，至少第一导体连接到至少一些所述栅极，以及至少第二导体连接到所述至少一些所述沟道; 以及形成在所述互连层上的电感器，所述电感器至少包括布置在层上的导体。

3. 发明申请

US20160322943A1 CIRCUITS FOR LOW NOISE AMPLIFIERS 有权
标题翻译：低噪声放大器电路
公开(公告)号：US20160322943A1
公开(公告)日：2016-11-03
申请号：US15107863
申请日：2014-12-24
申请人： Baradwaj VIGRAHAM , Peter R. KINGET
发明人： Baradwaj VIGRAHAM , Peter R. KINGET
IPC分类号： H03F3/193
CPC分类号： H03F3/193 , H03F1/565 , H03F3/19 , H03F3/211 , H03F2200/222 , H03F2200/294 , H03F2200/541 , H03F2200/78 , H03H11/28
摘要： Low noise amplifiers (LNAs) are provided, the LNAs comprising: a common gate matching network; a capacitord; a resistord; a coild, wherein a side1 of coild is coupled to a side1 of capacitord, a side1 of resistord, and a V+ and a side2 of the coild is coupled to a side2 of capacitord, a side2 of resistord, and a network input; a capacitors; a resistors; a coils, wherein a side1 of coils is coupled to an LNA input, a side1 of capacitors, a side1 of resistors, and a network output and a side2 of coils is coupled to a side2 of the capacitors, a side2 of resistors, and ground; and an output coil that is magnetically coupled to coild and coils and having a side1 coupled to a first terminal of an LNA output and a side2 coupled to a second terminal of the LNA output.
摘要翻译：提供低噪声放大器（LNA），LNA包括：公共门匹配网络; 一个电容; 抵抗者 coild，其中coild的side1耦合到电容的一侧，电阻的一侧，以及电阻的V +和侧面2耦合到电容的侧面2，电阻的侧面2和网络输入; 电容器电阻器线圈，其中线圈的侧面1耦合到LNA输入，电容器的侧面1，电阻器的侧面1以及网络输出端和线圈的侧面2耦合到电容器的侧面2，电阻器的侧面2和接地 ; 以及输出线圈，其被磁耦合到共线圈和线圈，并且具有耦合到LNA输出的第一端子的侧面1和耦合到LNA输出端的第二端子的侧面2。

4. 发明申请

US20080180187A1 SYSTEMS AND METHODS FOR REDUCING CIRCUIT AREA 有权
标题翻译：减少电路面积的系统和方法
公开(公告)号：US20080180187A1
公开(公告)日：2008-07-31
申请号：US11943287
申请日：2007-11-20
申请人： Peter R. KINGET , Frank ZHANG
发明人： Peter R. KINGET , Frank ZHANG
IPC分类号： G01D5/20 , H01F5/00
CPC分类号： H01L23/5227 , H01F2017/0046 , H01F2017/008 , H01F2021/125 , H01L27/0207 , H01L27/0727 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.
摘要翻译：提供了减少电路面积的方法和系统。一些实施例提供了电子设备，其包括由具有两个端部的路径形成的电感器，所述两个端部基本围绕围绕中心区域的平面环绕，其中所述路径在至少两个点处与其自身交叉，并且其中所述路径限定所述电感器的外边界; 以及位于电感器的外边界内并且基本上在平面内或与平面相邻的电路。其他实施例提供了电子设备，其包括由具有两个端部的路径形成的电感器，所述两个端部基本围绕围绕中心区域的平面环绕，其中所述路径限定所述电感器的外边界; 以及位于电感器的外边界内并且基本上在该平面内或与该平面相邻的电路，并且其中该电路包括一个信号路径，该信号路径是耙状的并以大致垂直的角度穿过该电感器的路径。

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