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1. 发明授权

US08836416B2 Tuning circuitry and method for active filters 有权
标题翻译：有源滤波器的调谐电路和方法
公开(公告)号：US08836416B2
公开(公告)日：2014-09-16
申请号：US13755207
申请日：2013-01-31
申请人： Jianxun Fan , Robert C. Glenn
发明人： Jianxun Fan , Robert C. Glenn
IPC分类号： H03K5/00
CPC分类号： H03K5/00 , H03K5/2481 , H03K5/249
摘要： Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.
摘要翻译：本发明的实施例可以包括具有可编程组件的滤波器，调谐信号发生器，比较器和反馈系统。调谐信号发生器可以将第一和第二测试信号输入到滤波器中，并且比较器可以响应每个相应的信号对滤波器的输出进行采样。然后，比较器可以将采样输出与预定值进行比较。响应于比较器的输出，反馈系统可以改变滤波器的可编程组件，直到可编程组件的搜索耗尽，产生第一和第二调谐结果。最后，反馈系统可以基于第一和第二调谐结果确定最终调谐结果。因此，滤波器的实际转角频率可以在期望转角频率的可接受范围内。

2. 发明授权

US08081837B2 Image sensor array leakage and dark current compensation 有权
标题翻译：图像传感器阵列泄漏和暗电流补偿
公开(公告)号：US08081837B2
公开(公告)日：2011-12-20
申请号：US11349840
申请日：2006-02-07
申请人： Robert C. Glenn , Edward S. Milligan
发明人： Robert C. Glenn , Edward S. Milligan
IPC分类号： G06K9/40
CPC分类号： H04N5/361 , H01L27/14601 , H04N5/359 , H04N5/374
摘要： Apparatus, systems and methods for image sensor leakage and dark current compensation are disclosed. In one implementation, a system comprises an imaging device including imaging pixels and two or more dark pixels, processing logic coupled to the imaging device, and an antenna coupled to the processing logic through an input/output (I/O) interface.
摘要翻译：公开了用于图像传感器泄漏和暗电流补偿的装置，系统和方法。在一个实现中，系统包括成像装置，其包括成像像素和两个或更多个暗像素，耦合到成像装置的处理逻辑，以及通过输入/输出（I / O）接口耦合到处理逻辑的天线。

3. 发明授权

US07167533B2 Apparatus and method for communication link receiver having adaptive clock phase shifting 失效
标题翻译：具有自适应时钟相移的通信链路接收机的装置和方法
公开(公告)号：US07167533B2
公开(公告)日：2007-01-23
申请号：US09895481
申请日：2001-06-30
申请人： Robert C. Glenn , Neil P. Kelly
发明人： Robert C. Glenn , Neil P. Kelly
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/0037 , H04L7/0041
摘要： A method is described that includes sampling data at a plurality of different relative phase positions between a clock signal and a data signal. The method also includes separately adjusting both the data signal's phase position and the clock signal's phase position to change the relative phase positions between the clock signal and the data signal at which data is sampled. Circuitry capable of performing the method is also described.
摘要翻译：描述了一种方法，其包括在时钟信号和数据信号之间的多个不同相对相位位置采样数据。该方法还包括分别调整数据信号的相位位置和时钟信号的相位位置，以改变时钟信号与采样数据的数据信号之间的相对相位。还描述了能够执行该方法的电路。

4. 发明授权

US07064618B2 PLL with swappable tuning loops 失效
标题翻译： PLL具有可交换调谐环
公开(公告)号：US07064618B2
公开(公告)日：2006-06-20
申请号：US10675152
申请日：2003-09-29
申请人： Robert C. Glenn
发明人： Robert C. Glenn
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03L7/0891 , H03L7/093 , H03L2207/06
摘要： Some embodiments provide a switch capacitor circuit to generate a first output capacitance based on a control signal, a main loop circuit to generate an output signal based on the control signal, and an oscillating circuit to generate an oscillating signal, a frequency of the oscillating signal based at least on the first output capacitance and the output signal.
摘要翻译：一些实施例提供开关电容器电路，以基于控制信号产生第一输出电容，基于控制信号产生输出信号的主环路电路和产生振荡信号的振荡电路，振荡信号的频率至少基于第一输出电容和输出信号。

5. 发明授权

US06639438B2 Apparatus and method for communication link having parallel signal detect with hysteresis 失效
标题翻译：具有滞后的并行信号检测的通信链路的装置和方法
公开(公告)号：US06639438B2
公开(公告)日：2003-10-28
申请号：US09895998
申请日：2001-06-30
申请人： Robert C. Glenn , Sumant Ranganathan
发明人： Robert C. Glenn , Sumant Ranganathan
IPC分类号： H03L700
CPC分类号： H04L25/06
摘要： A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.
摘要翻译：描述了一种涉及通过滞后比较器引导信号的方法。然后，响应于该信号确定迟滞比较器的输出信号是AC信号还是DC信号。然后，如果滞后比较器输出信号对应于DC信号，则去激活接收信号的信号接收单元; 或者如果滞后比较器输出信号对应于AC信号，则激活信号接收单元。

6. 发明申请

US20180013406A1 WIDE RANGE PROGRAMMABLE RESISTOR FOR DISCRETE LOGARITHMIC CONTROL, AND TUNING CIRCUIT FOR VARIABLE GAIN ACTIVE FILTER USING SAME 审中-公开
公开(公告)号：US20180013406A1
公开(公告)日：2018-01-11
申请号：US15204673
申请日：2016-07-07
申请人： Alexandru Aurelian Ciubotaru , Robert C. Glenn
发明人： Alexandru Aurelian Ciubotaru , Robert C. Glenn
IPC分类号： H03H11/12
CPC分类号： H03H11/1291 , H03H5/12 , H03H2210/017 , H03H2210/028
摘要： A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, −6 dB) relative to the maximum resistance value. Coarse increments of −6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.

7. 发明授权

US07409021B2 Voltage controller for a highly linear phase interpolator 有权
标题翻译：用于高线性相位内插器的电压控制器
公开(公告)号：US07409021B2
公开(公告)日：2008-08-05
申请号：US10039374
申请日：2002-01-02
申请人： Robert C. Glenn
发明人： Robert C. Glenn
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0812 , H03L7/091 , H04L7/0025
摘要： An arrangement for generating control signals is provided. Embodiments provides a method, apparatus, system, and machine-readable medium to generate substantially linear, analog control signals to adjust amplitude contributions of phases of a reference clock signal to facilitate interpolation of a changing phase of an interpolated clock signal with substantially analog transitions.
摘要翻译：提供了一种用于产生控制信号的装置。实施例提供了一种方法，装置，系统和机器可读介质，以生成基本上线性的模拟控制信号，以调整基准时钟信号的相位的幅度贡献，以便于以基本模拟转换内插插值时钟信号。

8. 发明申请

US20070285547A1 CMOS image sensor array optimization for both bright and low light conditions 审中-公开
标题翻译： CMOS图像传感器阵列优化亮光和低光条件
公开(公告)号：US20070285547A1
公开(公告)日：2007-12-13
申请号：US11443554
申请日：2006-05-30
申请人： Edward S. Milligan , Robert C. Glenn
发明人： Edward S. Milligan , Robert C. Glenn
IPC分类号： H04N5/335
CPC分类号： H04N5/3559 , H01L27/14609 , H01L27/14645 , H04N5/347 , H04N5/35563
摘要： Apparatus, systems and methods for CMOS image sensor array optimization for both bright and low light applications are disclosed. In one implementation, an apparatus includes an imaging array, the array including at least pixels of a first type having a first charge storage capacity and pixels of a second type having a second charge storage capacity. Other implementations are disclosed.
摘要翻译：公开了用于亮光和低光应用的CMOS图像传感器阵列优化的装置，系统和方法。在一个实现中，一种装置包括成像阵列，所述阵列至少包括具有第一电荷存储容量的第一类型的像素和具有第二电荷存储容量的第二类型的像素。公开了其他实现。

9. 发明授权

US07203259B2 Phase interpolator 失效
标题翻译：相位插值器
公开(公告)号：US07203259B2
公开(公告)日：2007-04-10
申请号：US10039253
申请日：2002-01-02
申请人： Robert C. Glenn , Michael W. Altmann
发明人： Robert C. Glenn , Michael W. Altmann
IPC分类号： G01R29/00 , H03L7/00 , H04L7/00
CPC分类号： H04L7/033 , H03L7/0812 , H03L7/091 , H04L7/0337
摘要： An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.
摘要翻译：一种用于产生时钟信号的装置。实施例提供了一种内插参考时钟信号的相位以输出内插时钟信号的方法，装置，系统和机器可读介质。一些实施例可将时钟信号输出为用于基于相位插值器的时钟恢复系统的恢复时钟信号。许多实施例可以基本上模拟转换内插内插时钟信号的变化相位。

10. 发明授权

US07197101B2 Phase interpolator based clock recovering 失效
标题翻译：基于相位内插器的时钟恢复
公开(公告)号：US07197101B2
公开(公告)日：2007-03-27
申请号：US10039016
申请日：2002-01-02
申请人： Robert C. Glenn , Michael W. Altmann
发明人： Robert C. Glenn , Michael W. Altmann
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a clock signal for clocked data based on a local clock signal. In some embodiments, the local clock signal may also be used to transmit the clocked data.
摘要翻译：提供了一种用于基于相位内插器的时钟恢复系统，相位内插器和用于高线性相位内插器系统的电压控制器的装置。实施例包括一种方法，装置，系统和机器可读介质，用于基于本地时钟信号恢复用于时钟数据的时钟信号。在一些实施例中，本地时钟信号也可以用于发送计时数据。

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