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1. 发明申请

US20050027524A1 System and method for disambiguating phonetic input 有权
标题翻译：消除语音输入的系统和方法
公开(公告)号：US20050027524A1
公开(公告)日：2005-02-03
申请号：US10631543
申请日：2003-07-30
申请人： Jianchao Wu , Jenny Lai , Lian He , Pim Meurs , Keng Wong , Lu Zhang
发明人： Jianchao Wu , Jenny Lai , Lian He , Pim Meurs , Keng Wong , Lu Zhang
IPC分类号： G10L15/18 , G10L15/26
CPC分类号： G10L15/187
摘要： A system and method for inputting Chinese characters using Pinyin without requiring the entry of a delimiter key between Pinyin entries in a reduced keyboard is disclosed. The system searches for all possible single or multiple Pinyin spellings based on the entered Latin alphabets. Once the user has completed the inputting of the Pinyin spellings for desired Chinese phrase or characters, all possible matching phrases or characters are displayed on screen and off-screen due to screen size. The user then scrolls through a list of matching phrases or characters and selects the desired one by clicking.
摘要翻译：公开了一种使用拼音输入中文的系统和方法，而不需要在缩位键盘中的拼音条目之间输入分隔符键。系统根据输入的拉丁字母搜索所有可能的单个或多个拼音拼写。一旦用户完成输入所需中文短语或拼写字母的拼音拼写，则所有可能的匹配短语或字符由于屏幕大小而显示在屏幕和屏幕外。然后，用户滚动查找匹配的短语或字符的列表，然后通过单击选择所需的短语或字符。

2. 发明申请

US20070152760A1 Self-biased phased-locked loop 有权
标题翻译：自偏置锁相环
公开(公告)号：US20070152760A1
公开(公告)日：2007-07-05
申请号：US11321495
申请日：2005-12-29
申请人： Swee Tan , Keng Wong
发明人： Swee Tan , Keng Wong
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/0995 , H03L2207/06
摘要： In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.
摘要翻译：通常，在一个方面，本公开描述了一种锁相环电路。该电路包括具有第一控制输入，第二控制输入和第三控制输入的振荡器，其中第一控制输入，第二控制输入和第三控制输入用于控制振荡器的输出频率。电路还包括第一电荷泵和第二电荷泵。第一偏置发生器耦合到振荡器的第一控制输入并且可以接收来自第一电荷泵的电输入。第二偏置发生器耦合到振荡器的第二控制输入，并且可以接收来自第一电荷泵，第二电荷泵和第一偏置发生器的电输入。第三偏置发生器耦合到振荡器的第三控制输入端，并可接收来自第二电荷泵和第一偏置发生器的电输入。

3. 外观设计

USD483742S1 Remote controller holder 失效
公开(公告)号：USD483742S1
公开(公告)日：2003-12-16
申请号：US29167514
申请日：2002-09-17
申请人： Keng Wong
设计人： Keng Wong

4. 发明申请

US20060200694A1 Controlling sequence of clock distribution to clock distribution domains 有权
标题翻译：控制时钟分配到时钟分配域的顺序
公开(公告)号：US20060200694A1
公开(公告)日：2006-09-07
申请号：US11073294
申请日：2005-03-04
申请人： Michael Rifani , Vaughn Grossnickle , Keng Wong
发明人： Michael Rifani , Vaughn Grossnickle , Keng Wong
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls enabling the clock distribution to the CKDOMs according to the scheduled sequence.
摘要翻译：本发明的一个实施例是一种控制电路的时钟分配的技术。调度器根据电路的状态将时钟信号的时钟分布序列调度到电路中的多个时钟分配域（CKDOM）。控制器根据调度顺序控制对CKDOM的时钟分配。

5. 发明申请

US20060156040A1 Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device 有权
公开(公告)号：US20060156040A1
公开(公告)日：2006-07-13
申请号：US10855268
申请日：2004-05-26
申请人： Alon Naveh , Roman Surgutchik , Stephen Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng Wong
发明人： Alon Naveh , Roman Surgutchik , Stephen Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng Wong
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

6. 外观设计

USD478899S1 Remote controller holder 失效
公开(公告)号：USD478899S1
公开(公告)日：2003-08-26
申请号：US29167511
申请日：2002-09-17
申请人： Keng Wong
设计人： Keng Wong

7. 发明授权

US07154320B2 Frequency-based slope-adjustment circuit 失效
标题翻译：基于频率的斜坡调整电路
公开(公告)号：US07154320B2
公开(公告)日：2006-12-26
申请号：US11093643
申请日：2005-03-29
申请人： Usman A. Mughal , Keng Wong
发明人： Usman A. Mughal , Keng Wong
IPC分类号： H03H11/26
CPC分类号： H03K5/12 , H03K5/133 , H03K2005/00039 , H03K2005/00286
摘要： A method and apparatus for a frequency-based slope-adjustment circuit block are described herein.
摘要翻译：这里描述了一种基于频率的斜率调节电路块的方法和装置。

8. 发明申请

US20060267646A1 Self-biased phased-locked loop 失效
标题翻译：自偏置锁相环
公开(公告)号：US20060267646A1
公开(公告)日：2006-11-30
申请号：US11140684
申请日：2005-05-31
申请人： Swee Tan , Keng Wong
发明人： Swee Tan , Keng Wong
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0995 , H03L7/10
摘要： In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.
摘要翻译：通常，在一个方面，本公开描述了一种锁相环电路。该电路包括具有第一控制输入和第二控制输入的振荡器，其中第一控制输入和第二控制输入用于控制振荡器的输出频率。电路还包括第一电荷泵和第二电荷泵。第一偏置发生器耦合到振荡器的第一控制输入，并且可以接收来自第一电荷泵和第二电荷泵的电输入。第二偏置发生器耦合到振荡器的第二控制输入端并且可以接收来自第二电荷泵和第一偏置发生器的电输入。

9. 发明申请

US20060091964A1 Method and apparatus for jitter reduction in phase locked loops 失效
公开(公告)号：US20060091964A1
公开(公告)日：2006-05-04
申请号：US11303682
申请日：2005-12-15
申请人： Keng Wong , Chee Lim
发明人： Keng Wong , Chee Lim
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/095
摘要： A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

10. 发明授权

US06320424B1 Method of providing and circuit for providing phase lock loop frequency overshoot control 失效
标题翻译：提供和提供锁相环频率过冲控制的方法
公开(公告)号：US06320424B1
公开(公告)日：2001-11-20
申请号：US09609331
申请日：2000-06-30
申请人： Nasser A. Kurd , Yi Lu , Keng Wong
发明人： Nasser A. Kurd , Yi Lu , Keng Wong
IPC分类号： G01R2500
CPC分类号： H03L7/18 , H03L7/0891
摘要： A phase lock loop system is provided that includes a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal. The phase lock loop system may include a width control circuit to alter a width of the first control signal and to produce an altered first control signal.
摘要翻译：提供一种锁相环系统，其包括相位频率检测器装置，用于接收参考时钟信号和反馈时钟信号，并提供第一控制信号和第二控制信号。锁相环系统可以包括宽度控制电路，以改变第一控制信号的宽度并产生改变的第一控制信号。

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