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1. 发明申请

US20080150949A1 QUICK PIXEL RENDERING PROCESSING 有权
标题翻译：快速像素渲染处理
公开(公告)号：US20080150949A1
公开(公告)日：2008-06-26
申请号：US11615379
申请日：2006-12-22
申请人： Jian Wei , Chebul (David) Wu , James M. Brown
发明人： Jian Wei , Chebul (David) Wu , James M. Brown
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M×N sub-screen tasks. Based on system profiling, M and N may be varied.
摘要翻译：三维（3D）图形流水线，其并行和独立地处理最后阶段（像素渲染）中的子屏幕的像素。子屏幕任务存储在共享内存中的列表中。共享存储器被指定用于像素渲染的多个处理线程访问。处理线程以有序的方式占用和锁定子屏幕任务，并处理任务以创建用于在屏幕上显示的位图。通过将其上叠加有顶点信息的显示区域划分为M×N子画面任务来创建任务。基于系统分析，M和N可以变化。

2. 发明授权

US07940261B2 Automatic load balancing of a 3D graphics pipeline 有权
标题翻译： 3D图形管道的自动负载平衡
公开(公告)号：US07940261B2
公开(公告)日：2011-05-10
申请号：US11621917
申请日：2007-01-10
申请人： Jian Wei , James M. Brown , David Wu
发明人： Jian Wei , James M. Brown , David Wu
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T1/20
摘要： A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.
摘要翻译：一种设备具有用于处理三维（3D）图形流水线的顶点处理阶段，子屏幕划分阶段和像素渲染阶段的处理器。该处理器包括处理线程，其平衡3D图形流水线的工作负载，通过对像素渲染阶段的处理优先于其他阶段。并行和独立运行的每个处理线程检查子屏幕任务的任务列表中的任务级别。如果该级别低于阈值，则清空或子屏幕任务都被锁定，则处理线程循环到顶点处理阶段。否则，处理线程在像素渲染阶段处理子屏幕任务。

3. 发明申请

US20080165199A1 AUTOMATIC LOAD BALANCING OF A 3D GRAPHICS PIPELINE 有权
标题翻译： 3D图形管道的自动负载平衡
公开(公告)号：US20080165199A1
公开(公告)日：2008-07-10
申请号：US11621917
申请日：2007-01-10
申请人： Jian Wei , James M. Brown , David Wu
发明人： Jian Wei , James M. Brown , David Wu
IPC分类号： G06T1/20
CPC分类号： G06T15/005 , G06T1/20
摘要： A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.
摘要翻译：一种设备具有用于处理三维（3D）图形流水线的顶点处理阶段，子屏幕划分阶段和像素渲染阶段的处理器。该处理器包括处理线程，其平衡3D图形流水线的工作负载，通过对像素渲染阶段的处理优先于其他阶段。并行和独立运行的每个处理线程检查子屏幕任务的任务列表中的任务级别。如果该级别低于阈值，则清空或子屏幕任务都被锁定，则处理线程循环到顶点处理阶段。否则，处理线程在像素渲染阶段处理子屏幕任务。

4. 发明授权

US08207972B2 Quick pixel rendering processing 有权
标题翻译：快速像素渲染处理
公开(公告)号：US08207972B2
公开(公告)日：2012-06-26
申请号：US11615379
申请日：2006-12-22
申请人： Jian Wei , Chehui Wu , James M Brown
发明人： Jian Wei , Chehui Wu , James M Brown
IPC分类号： G06F15/00 , G06F1/00 , G06F15/80 , G06T1/20 , G06F9/46
CPC分类号： G06T15/005
摘要： A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M×N sub-screen tasks. Based on system profiling, M and N may be varied.
摘要翻译：三维（3D）图形流水线，其并行和独立地处理最后阶段（像素渲染）中的子屏幕的像素。子屏幕任务存储在共享内存中的列表中。共享存储器被指定用于像素渲染的多个处理线程访问。处理线程以有序的方式占用和锁定子屏幕任务，并处理任务以创建用于在屏幕上显示的位图。通过将具有叠加在其上的顶点信息的显示区域划分为M×N个子屏幕任务来创建任务。基于系统分析，M和N可以变化。

5. 发明授权

US08755444B2 Two-stage entropy decoding 失效
标题翻译：两阶段熵解码
公开(公告)号：US08755444B2
公开(公告)日：2014-06-17
申请号：US12851784
申请日：2010-08-06
申请人： Jian Wei , Kai Wang , Toshiaki Yoshino
发明人： Jian Wei , Kai Wang , Toshiaki Yoshino
IPC分类号： H04N7/26 , H04N7/50
CPC分类号： H04N19/00472 , H04N19/40 , H04N19/428 , H04N19/44 , H04N19/61 , H04N19/91
摘要： The subject matter of this specification can be implemented in, among other things, a method of decoding video data that includes decoding compressed input video data using a first entropy coding technique to obtain first decoded data. The method further includes re-encoding the first decoded data using a second entropy coding technique that is different from the first entropy coding technique to obtain re-encoded data. The method further includes storing the re-encoded data in a storage device. The method further includes decoding the re-encoded data using the second entropy coding technique to obtain second decoded data.
摘要翻译：本说明书的主题还可以实现一种解码视频数据的方法，该方法包括使用第一熵编码技术解码压缩输入视频数据，以获得第一解码数据。该方法还包括使用与第一熵编码技术不同的第二熵编码技术对第一解码数据进行重新编码以获得重新编码的数据。该方法还包括将重新编码的数据存储在存储设备中。该方法还包括使用第二熵编码技术解码重新编码的数据，以获得第二解码数据。

6. 发明申请

US20090197474A1 Electronic assembly with foldable connector 审中-公开
标题翻译：具有可折叠连接器的电子组件
公开(公告)号：US20090197474A1
公开(公告)日：2009-08-06
申请号：US12322453
申请日：2009-02-02
申请人： Jian Wei , Xiao-Li Li , Ping-Sheng Su
发明人： Jian Wei , Xiao-Li Li , Ping-Sheng Su
IPC分类号： H01R24/00
CPC分类号： H01R35/025 , H01R13/6658 , H01R13/7175 , H01R24/58 , H01R31/065 , H01R2103/00
摘要： An electronic assembly (100) includes a housing having a plurality of walls together defining a receiving space and an outlet defined in one of the walls and in communication to the receiving space; a connector (53) pivotally linked to the housing and projected outward of the housing via the outlet; a locking member (6) mounted to the housing, said locking member including a base portion (60) having a first side and a second side opposite to the first side, a stopper portion (62) formed on the first side and extending into the receiving opening, a resilient member (61) arranged adjacent to the second side for exerting a resilient force to the base portion, and a handling portion (521) attached to a rear portion of the connector and disposed proximate to the outlet of the one wall.
摘要翻译：电子组件（100）包括壳体，其具有多个壁，所述多个壁一起限定容纳空间和限定在所述壁之一中并与所述容纳空间连通的出口; 连接器（53），其经由所述出口枢转地连接到所述壳体并突出到所述壳体的外部; 安装在所述壳体上的锁定件（6），所述锁定件包括具有第一侧和与所述第一侧相对的第二侧的基部（60），形成在所述第一侧上并延伸到所述第一侧的止挡部分接收开口，邻近所述第二侧设置用于向所述基部施加弹力的弹性构件（61），以及附接到所述连接器的后部并且邻近所述一个壁的出口设置的操纵部分（521）。

7. 发明授权

US06683817B2 Direct memory swapping between NAND flash and SRAM with error correction coding 有权
标题翻译：通过纠错编码直接在NAND闪存和SRAM之间进行存储交换
公开(公告)号：US06683817B2
公开(公告)日：2004-01-27
申请号：US10081503
申请日：2002-02-21
申请人： Jian Wei , Inyup Kang , Julio Arceo , Jalal Husseini , Tao Li , Bruce Meagher , Richard Higgins , Moto Oishi , Brian Rodrigues
发明人： Jian Wei , Inyup Kang , Julio Arceo , Jalal Husseini , Tao Li , Bruce Meagher , Richard Higgins , Moto Oishi , Brian Rodrigues
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G06F3/0601 , G06F11/1068 , G06F13/1684 , G06F2003/0692 , G11C11/005
摘要： Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.
摘要翻译：通过纠错编码（ECC）支持NAND Flash和SRAM之间的直接内存交换的内存架构和技术。在具体设计中，存储器架构包括可操作以提供数据存储的第一存储单元（例如，SRAM），可操作地提供数据存储的第二存储单元（例如，NAND闪存），EMI单元实现在ASIC内并且可操作以提供用于存储单元的控制信号，以及耦合到两个存储单元和EMI单元的数据总线。两个存储单元在ASIC外部实现，并且当另一存储单元被EMI单元访问时，每个存储单元可操作以经由数据总线从另一个存储单元存储数据。 EMI单元可以包括ECC单元，其用于对从第二存储单元传送到/从第二存储单元的数据执行块编码。

8. 发明授权

US08873924B2 Fiber optic cabinet 有权
标题翻译：光纤柜
公开(公告)号：US08873924B2
公开(公告)日：2014-10-28
申请号：US13696470
申请日：2010-06-23
申请人： Jian Wei , Bin Lu , Bin Yu , Yifeng Cui , Peiyou Xiong , Yingliang Peng , Zhiyong Xu , Yingyu Wang
发明人： Jian Wei , Bin Lu , Bin Yu , Yifeng Cui , Peiyou Xiong , Yingliang Peng , Zhiyong Xu , Yingyu Wang
IPC分类号： G02B6/36 , G02B6/44
CPC分类号： G02B6/4401 , G02B6/4442
摘要： The present invention relates to a fiber optic telecommunication cabinet for use in fiber optic telecommunication networks. The fiber optic telecommunication cabinet comprises a base and a housing. The base has a plurality of ports passing through the base to allow passage telecommunication cables into the fiber optic cabinet. The fiber optic telecommunication cabinet further includes an optical fiber termination block attached to the base. The optical fiber termination block has a plurality of optical modules supported by the mounting frame, wherein the optical modules may be rotated in a plane perpendicular to the longitudinal direction of the fiber optic telecommunication cabinet from a first storage position to a second accessible position.
摘要翻译：本发明涉及一种用于光纤通信网络的光纤通信柜。光纤通信柜包括基座和外壳。基座具有穿过基座的多个端口，以允许将通信电缆通入光纤机柜。光纤通信柜还包括连接到基座的光纤终端块。光纤终端块具有由安装框架支撑的多个光学模块，其中，光学模块可以在垂直于光纤通信柜的纵向方向的平面中从第一存储位置旋转到第二可访问位置。

9. 发明授权

US07641483B2 Electronic assembly with foldable connector 失效
标题翻译：具有可折叠连接器的电子组件
公开(公告)号：US07641483B2
公开(公告)日：2010-01-05
申请号：US12322461
申请日：2009-02-02
申请人： Jian Wei , Xiao-Li Li , Ping-Sheng Su
发明人： Jian Wei , Xiao-Li Li , Ping-Sheng Su
IPC分类号： H01R13/60
CPC分类号： H01R24/58 , H01R13/6658 , H01R31/06 , H01R2107/00
摘要： An electronic assembly (100) includes a housing having a plurality of walls together defining a receiving space and an outlet defined in one of the walls and in communication to the receiving space; a connector (53) pivotally linked to the housing and projected outward of the housing via the outlet; a locking member (6) mounted to the housing, said locking member including a base portion (60) having a first side and a second side opposite to the first side, a stopper portion (62) formed on the first side and extending into the receiving opening, and a resilient member (61) arranged adjacent to the second side for exerting a resilient force to the base portion.
摘要翻译：电子组件（100）包括壳体，其具有多个壁，所述多个壁一起限定容纳空间和限定在所述壁之一中并与所述容纳空间连通的出口; 连接器（53），其经由所述出口枢转地连接到所述壳体并突出到所述壳体的外部; 安装在所述壳体上的锁定件（6），所述锁定件包括具有第一侧和与所述第一侧相对的第二侧的基部（60），形成在所述第一侧上并延伸到所述第一侧以及与所述第二侧相邻布置的用于向所述基部施加弹性力的弹性构件（61）。

10. 发明申请

US20080313442A1 DEBUGGING TECHNIQUES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 审中-公开
标题翻译：可编程集成电路的调试技术
公开(公告)号：US20080313442A1
公开(公告)日：2008-12-18
申请号：US11762647
申请日：2007-06-13
申请人： Jian Wei , Manojkumar Pyla , Xufeng Chen
发明人： Jian Wei , Manojkumar Pyla , Xufeng Chen
IPC分类号： G06F9/30
CPC分类号： G06F11/2236
摘要： Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices.
摘要翻译：描述了用于调试可编程集成电路的技术。实施例包括使用执行测试程序的远程计算机启动集成电路中的指令高速缓存未命中的步骤; 在指令高速缓存未命中事件期间，使用测试程序提供的测试指令来代替应用程序中的指令; 并根据其对测试指令的响应分析调试集成电路。在示例性应用中，这样的技术用于调试无线通信片上系统的图形处理器以及其他可编程集成电路器件。

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