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1. 发明公开

US20240202869A1 REAL-TIME NEURAL LIGHT FIELD ON MOBILE DEVICES 审中-公开
公开(公告)号：US20240202869A1
公开(公告)日：2024-06-20
申请号：US18080959
申请日：2022-12-14
申请人： Jian Ren , Pavlo Chemerys , Vladislav Shakhrai , Ju Hu , Denys Makoviichuk , Sergey Tulyakov , Junli Cao
发明人： Jian Ren , Pavlo Chemerys , Vladislav Shakhrai , Ju Hu , Denys Makoviichuk , Sergey Tulyakov , Junli Cao
IPC分类号： G06T3/40
CPC分类号： G06T3/4046 , G06T3/4053
摘要： A neural light field (NeLF) that runs real-time on mobile devices for neural rendering of three dimensional (3D) scenes, referred to as MobileR2L. The MobileR2L architecture runs efficiently on mobile devices with low latency and small size, and it achieves high-resolution generation while maintaining real-time inference for both synthetic and real-world 3D scenes on mobile devices. The MobileR2L has a network backbone including a convolutional layer embedding an input image at a resolution, residual blocks uploading the embedded image, and super-resolution modules receiving the uploaded embedded image and rendering an output image having a higher resolution than the embedded image. The convolution layer generates a number of rays equal to a number of pixels in the input image, where a partial number of the rays is uploaded to the super-resolution modules.

2. 发明公开

US20240203114A1 VISION TRANSFORMER FOR MOBILENET SIZE AND SPEED 审中-公开
公开(公告)号：US20240203114A1
公开(公告)日：2024-06-20
申请号：US18080993
申请日：2022-12-14
申请人： Jian Ren , Yanyu Li , Ju Hu , Yang Wen , Georgios Evangelidis , Sergey Tulyakov , Kamyar Salahi
发明人： Jian Ren , Yanyu Li , Ju Hu , Yang Wen , Georgios Evangelidis , Sergey Tulyakov , Kamyar Salahi
IPC分类号： G06V10/94 , G06V10/77
CPC分类号： G06V10/95 , G06V10/7715
摘要： A mobile vision transformer network for use on mobile devices, such as smart eyewear devices and other augmented reality (AR) and virtual reality (VR) devices. The mobile vision transformer network considers factors including number of parameters, latency, and model performance, as they reflect disk storage, mobile frames per second (FPS), and application quality, respectively. The mobile vision transformer network processes images, e.g., for image classification, segmentation, and detection. The mobile vision transformer network has a fine-grained architecture including a search algorithm performing latency-driven slimming that jointly improves model size and speed.

3. 发明公开

US20240020948A1 EFFICIENTFORMER VISION TRANSFORMER 审中-公开
公开(公告)号：US20240020948A1
公开(公告)日：2024-01-18
申请号：US17865178
申请日：2022-07-14
申请人： Jian Ren , Yang Wen , Ju Hu , Georgios Evangelidis , Sergey Tulyakov , Yanyu Li , Geng Yuan
发明人： Jian Ren , Yang Wen , Ju Hu , Georgios Evangelidis , Sergey Tulyakov , Yanyu Li , Geng Yuan
IPC分类号： G06V10/764 , G06V10/82 , G06V10/44
CPC分类号： G06V10/764 , G06V10/82 , G06V10/454
摘要： A vision transformer network having extremely low latency and usable on mobile devices, such as smart eyewear devices and other augmented reality (AR) and virtual reality (VR) devices. The transformer network processes an input image, and the network includes a convolution stem configured to patch embed the image. A first stack of stages including at least two stages of 4-Dimension (4D) metablocks (MBs) (MB4D) follow the convolution stem. A second stack of stages including at least two stages of 3-Dimension MBs (MB3D) follow the MB4D stages. Each of the MB4D stages and each of the MB3D stages include different layer configurations, and each of the MB4D stages and each of the MB3D stages include a token mixer. The MB3D stages each additionally include a multi-head self attention (MHSA) processing block.

4. 发明申请

US20120049319A1 PARASITIC PIN DEVICE IN A BICMOS PROCESS AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译： BICMOS工艺中的PARASITIC PIN DEVICE及其制造方法
公开(公告)号：US20120049319A1
公开(公告)日：2012-03-01
申请号：US13218316
申请日：2011-08-25
申请人： Wensheng Qian , Ju Hu
发明人： Wensheng Qian , Ju Hu
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L27/0635 , H01L21/8249
摘要： A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.
摘要翻译：公开了一种BiCMOS工艺中的寄生PIN器件。该器件形成在硅衬底上，其中有源区被浅沟槽隔离。该器件包括：N型区域，由分别形成在浅沟槽隔离氧化物层的底部并延伸到有源区域中的N型伪埋层构成; I型区域，由在有源区域形成并与N型区域接触的N型集电极注入区域构成; P型区域，由有源区域的表面上的P掺杂的本征基极外延层组成并与I型区域接触。本发明的器件具有低插入损耗和高隔离度。还公开了与现有BiCMOS工艺兼容的寄生PIN器件的制造方法。

5. 发明授权

US08476728B2 Parasitic PIN device in a BiCMOS process and manufacturing method of the same 有权
标题翻译：寄生PIN器件在BiCMOS工艺及其制造方法中的应用
公开(公告)号：US08476728B2
公开(公告)日：2013-07-02
申请号：US13218316
申请日：2011-08-25
申请人： Wensheng Qian , Ju Hu
发明人： Wensheng Qian , Ju Hu
IPC分类号： H01L31/102 , H01L29/66
CPC分类号： H01L27/0635 , H01L21/8249
摘要： A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.
摘要翻译：公开了一种BiCMOS工艺中的寄生PIN器件。该器件形成在硅衬底上，其中有源区被浅沟槽隔离。该器件包括：N型区域，由分别形成在浅沟槽隔离氧化物层的底部并延伸到有源区域中的N型伪埋层构成; I型区域，由在有源区域形成并与N型区域接触的N型集电极注入区域构成; P型区域，由有源区域的表面上的P掺杂的本征基极外延层组成并与I型区域接触。本发明的器件具有低插入损耗和高隔离度。还公开了与现有BiCMOS工艺兼容的寄生PIN器件的制造方法。

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