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1. 发明授权

US06358760B1 Method for amorphous silicon local interconnect etch 有权
标题翻译：非晶硅局部互连蚀刻方法
公开(公告)号：US06358760B1
公开(公告)日：2002-03-19
申请号：US09583552
申请日：2000-06-01
申请人： Jiahua Huang , Allison Holbrook , James H. Chiang , Sunny Cherian
发明人： Jiahua Huang , Allison Holbrook , James H. Chiang , Sunny Cherian
IPC分类号： H01L2100
CPC分类号： H01L21/32137
摘要： A silicon layer is etched using a plasma etcher equipped with an endpoint control device. CF4 and N2 are provided to the plasma etcher at lower flow rates than those typically used during fixed time etching processes. The endpoint control device monitors optical emissions from the etching chamber at a particular wavelength to detect a predetermined change in intensity. When the change in intensity is detected, the etching is terminated.
摘要翻译：使用配备有端点控制装置的等离子体蚀刻器蚀刻硅层。 CF4和N2以比在固定时间蚀刻工艺中通常使用的那些更低的流速提供给等离子体蚀刻机。端点控制装置监测来自蚀刻室的特定波长的光发射以检测预定的强度变化。当检测到强度变化时，终止蚀刻。

2. 发明授权

US06495853B1 Self-aligned gate semiconductor 有权
标题翻译：自对准栅极半导体
公开(公告)号：US06495853B1
公开(公告)日：2002-12-17
申请号：US09636333
申请日：2000-08-10
申请人： Allison Holbrook , Jiahua Huang , Sunny Cherian
发明人： Allison Holbrook , Jiahua Huang , Sunny Cherian
IPC分类号： H01L2906
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体晶片上形成隧道电介质层和栅极层，并且使用沟槽形成技术来限定浮动栅极结构。绝缘体沉积在沟槽中，由此栅极层和隧道介电层形成与隧道电介质自对准的栅极。

3. 发明授权

US06821713B1 Method for lateral trimming of spacers 失效
标题翻译：间隔件横向修剪方法
公开(公告)号：US06821713B1
公开(公告)日：2004-11-23
申请号：US10085242
申请日：2002-02-27
申请人： Allison Holbrook , Jiahua Huang , Sunny Cherian
发明人： Allison Holbrook , Jiahua Huang , Sunny Cherian
IPC分类号： G03F726
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/32137 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.
摘要翻译：提供间隔蚀刻修剪技术。该方法利用自限制蚀刻技术可控制地修整多层叠层间隔物。该方法可以使用具有低偏压功率的干蚀刻蚀刻机。干法蚀刻工艺也可以使用其它改进的参数，例如气流和各种压力。

4. 发明授权

US06383945B1 High selectivity pad etch for thick topside stacks 失效
标题翻译：用于厚顶层叠层的高选择性焊盘蚀刻
公开(公告)号：US06383945B1
公开(公告)日：2002-05-07
申请号：US09430465
申请日：1999-10-29
申请人： Jiahua Huang , Jeffrey A. Shields , Allison Holbrook
发明人： Jiahua Huang , Jeffrey A. Shields , Allison Holbrook
IPC分类号： H01L21203
CPC分类号： H01L24/03 , H01L21/31116 , H01L21/76804 , H01L24/02 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/04941 , H01L2924/13091
摘要： An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.
摘要翻译：对覆盖半导体器件的金属焊盘的厚的保护性顶层叠层膜进行了改进的蚀刻。本发明使用下游等离子体各向同性蚀刻来蚀刻顶层叠层膜。在一个实施例中，下游等离子体各向同性蚀刻用于仅蚀刻顶层叠层膜的一部分。使用随后的各向异性氧化物等离子体蚀刻来将剩余的顶层叠层膜蚀刻到金属焊盘。在另一个实施例中，下游等离子体各向同性蚀刻用于通过顶层叠层膜完全蚀刻到金属焊盘。本发明允许通过顶层叠层膜蚀刻大于5微米。

5. 发明授权

US06013156A Bubble monitor for semiconductor manufacturing 失效
标题翻译：用于半导体制造的气泡监测器
公开(公告)号：US06013156A
公开(公告)日：2000-01-11
申请号：US34084
申请日：1998-03-03
申请人： Allison Holbrook , Jiahua Huang , Aaron A. Fernandes
发明人： Allison Holbrook , Jiahua Huang , Aaron A. Fernandes
IPC分类号： H01L21/00 , C23F1/02
CPC分类号： H01L21/67253 , H01L21/67086
摘要： Apparatus for monitoring the hydrogen peroxide concentration in a sulfuric acid bath used to remove photoresist from semiconductor wafers uses the amount of bubbles in the fluid mixture to signal the addition of hydrogen peroxide. The bubbles are directly related to the hydrogen peroxide in sulfuric acid mixture. The bubbles are sensed by a light source and photoelectric sensor connected to a threshold adjustment control which controls a metering solenoid valve to add hydrogen peroxide from a reservoir to the bath when the bubbles decrease.
摘要翻译：用于监测用于从半导体晶片去除光致抗蚀剂的硫酸浴中的过氧化氢浓度的装置使用流体混合物中的气泡量来表示加入过氧化氢。气泡与硫酸混合物中的过氧化氢直接相关。气泡由光源和连接到阈值调节控制器的光电传感器感测到，当气泡减少时，控制计量电磁阀将过氧化氢从储存器添加到浴中。

6. 发明授权

US06297065B1 Method to rework device with faulty metal stack layer 失效
标题翻译：使用故障金属堆叠层对设备进行返修的方法
公开(公告)号：US06297065B1
公开(公告)日：2001-10-02
申请号：US09229006
申请日：1999-01-12
申请人： Jiahua Huang , Pei-Yuan Gao , Anne E. Sanderfer
发明人： Jiahua Huang , Pei-Yuan Gao , Anne E. Sanderfer
IPC分类号： H01L2166
CPC分类号： H01L22/26 , H01L21/485 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.
摘要翻译：一种制造半导体晶片的方法，其中在部分完成的半导体晶片上的层间电介质层的表面上形成金属层，如果确定金属层有故障，则去除有缺陷的金属层的表面层间电介质的层被降低到形成在层间电介质层中的金属插塞的顶部之下，金属插塞的顶部平坦化到层间电介质层的表面，金属层在层间电介质的表面上重整。如果金属层被确定为良好，则金属层被蚀刻。如果金属蚀刻有故障，则金属层被去除，层间电介质层被还原成在层间电介质层形成的插塞的顶部之下，金属插塞的顶部被平坦化到层层间电介质和金属层被重整。

7. 发明授权

US06500768B1 Method for selective removal of ONO layer 有权
标题翻译：选择性去除ONO层的方法
公开(公告)号：US06500768B1
公开(公告)日：2002-12-31
申请号：US09699531
申请日：2000-10-30
申请人： Jeffrey A. Shields , Jiahua Huang , Jean Yee-Mei Yang
发明人： Jeffrey A. Shields , Jiahua Huang , Jean Yee-Mei Yang
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.
摘要翻译：一种制造半导体器件的方法，该方法包括提供其上具有氧化物 - 氮化物 - 氧化物层的半导体衬底和覆盖氧化物 - 氮化物 - 氧化物层的图案化抗蚀剂层，其中氧化物 - 氮化物 - 氧化物层包括第一氧化物层，覆盖第一氧化物层的氮化物层和覆盖氮化物层的第二氧化物层。该方法还包括：在氧化物 - 氮化物 - 氧化物层上进行各向同性蚀刻以去除氧化物 - 氮化物 - 氧化物层的一部分。

8. 发明授权

US06647995B1 Method and system for eliminating post etch residues 失效
标题翻译：消除后蚀刻残留物的方法和系统
公开(公告)号：US06647995B1
公开(公告)日：2003-11-18
申请号：US09894569
申请日：2001-06-27
申请人： Jiahua Huang , Yue-Song He , Frank Mak
发明人： Jiahua Huang , Yue-Song He , Frank Mak
IPC分类号： B08B700
CPC分类号： H01L21/67069 , B08B7/0035 , H01J2237/3151 , H01L21/31116
摘要： A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.
摘要翻译：公开了一种用于消除后蚀刻残留物的方法和系统。在一个方法实施例中，本发明背诵设置具有粘附到其上的后蚀刻残留物的表面，靠近产生电子的电子束源。本方法实施例然后用电子轰击后蚀刻残留物，使得后蚀刻残留物从粘附有后蚀刻残余物的表面除去。

9. 发明授权

US06306707B1 Double layer hard mask process to improve oxide quality for non-volatile flash memory products 有权
标题翻译：双层硬掩模工艺，提高非挥发性闪存产品的氧化物质量
公开(公告)号：US06306707B1
公开(公告)日：2001-10-23
申请号：US09716659
申请日：2000-11-20
申请人： John Foster , Yue-Song He , Jiahua Huang
发明人： John Foster , Yue-Song He , Jiahua Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In the manufacture of an EPROM or EEPROM semiconductor device that includes a core region and a peripheral region, a nitride layer is formed over the core region and peripheral region, and an oxide layer is formed over the nitride layer. A layer of photoresist is provided over the oxide layer and is patterned to expose a portion of the oxide layer overlying the core region. A wet etch step is undertaken to remove the exposed portion of the oxide layer, using the patterned photoresist as a mask, and leaving exposed a portion of the nitride layer overlying the core region. After removal of the photoresist, the exposed portion of the nitride layer is etched by a wet etch step with hot phosphoric acid, using the pattered oxide layer as a mask.
摘要翻译：在制造包括芯区域和周边区域的EPROM或EEPROM半导体器件中，在芯区域和外围区域上形成氮化物层，并且在氮化物层上形成氧化物层。在氧化物层上提供一层光致抗蚀剂，并将其图案化以暴露覆盖芯区域的氧化物层的一部分。进行湿蚀刻步骤以使用图案化的光致抗蚀剂作为掩模去除氧化物层的暴露部分，并且将覆盖在核心区域上的氮化物层的一部分暴露出来。在去除光致抗蚀剂之后，使用图案化的氧化物层作为掩模，通过用热磷酸的湿蚀刻步骤蚀刻氮化物层的暴露部分。

10. 发明授权

US6153470A Floating gate engineering to improve tunnel oxide reliability for flash memory devices 失效
标题翻译：浮栅工程，以提高闪存器件的隧道氧化可靠性
公开(公告)号：US6153470A
公开(公告)日：2000-11-28
申请号：US374059
申请日：1999-08-12
申请人： Yue-Song He , Kent K. Chang , Jiahua Huang
发明人： Yue-Song He , Kent K. Chang , Jiahua Huang
IPC分类号： H01L21/28 , H01L29/423 , H01L29/49 , H01L21/336 , H01L21/8234 , H01L29/04 , H01L29/72 , H01L31/072
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/4916 , Y10S438/923
摘要： A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.
摘要翻译：一种形成浮动栅极以提高闪存器件的隧道氧化物可靠性的方法。提供具有源极，漏极和沟道区域的衬底。在衬底上形成隧道氧化物层。在隧道氧化物和沟道区域上形成浮栅，浮栅是多层的，并且具有夹在第一层和第三层之间的第二层。覆盖隧道氧化物层的浮置栅极的第一层包括未掺杂或轻掺杂的材料。第二层是高度掺杂的。第三层与电介质层直接接触，例如氧化物 - 氮化物 - 氧化物堆叠，并且由未掺杂或轻掺杂的材料制成。介电材料形成在浮动栅极上，并且控制栅极形成在电介质材料上。

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