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1. 发明申请

US20110313735A1 CIRCUIT DEVICE RELIABILITY SIMULATION SYSTEM 有权
标题翻译：电路设备可靠性仿真系统
公开(公告)号：US20110313735A1
公开(公告)日：2011-12-22
申请号：US12818655
申请日：2010-06-18
申请人： Jia-Lin Lo , Ke-Wei Su , Min-Chie Jeng , Feng-Ling Hsiao , Cheng Hsiao , Yi-Shun Huang , Yi-Chun Chen
发明人： Jia-Lin Lo , Ke-Wei Su , Min-Chie Jeng , Feng-Ling Hsiao , Cheng Hsiao , Yi-Shun Huang , Yi-Chun Chen
IPC分类号： G06F17/50 , G06F17/11 , G06F19/00
CPC分类号： G06F17/5036 , G01R31/2642 , G01R31/2648 , G06F2217/76 , G06F2217/82
摘要： The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.
摘要翻译：本公开提供了用于预测半导体可靠性的系统。在一个实施例中，用于预测半导体可靠性的方法包括接收半导体器件的劣化参数输入并使用劣化方程式根据劣化参数输入在短时间段内确定用于劣化的多个偏置相关斜率值。多个斜率值包括至少两个不同的斜率值，用于随着时间的推移而退化。系统累积多个斜率值，并且在长时间段内累积累积的斜率值，以确定半导体器件的应力效应。

2. 发明授权

US09141735B2 Circuit device reliability simulation system 有权
标题翻译：电路设备可靠性仿真系统
公开(公告)号：US09141735B2
公开(公告)日：2015-09-22
申请号：US12818655
申请日：2010-06-18
申请人： Jia-Lin Lo , Ke-Wei Su , Min-Chie Jeng , Feng-Ling Hsiao , Cheng Hsiao , Yi-Shun Huang , Yi-Chun Chen
发明人： Jia-Lin Lo , Ke-Wei Su , Min-Chie Jeng , Feng-Ling Hsiao , Cheng Hsiao , Yi-Shun Huang , Yi-Chun Chen
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： G06F17/5036 , G01R31/2642 , G01R31/2648 , G06F2217/76 , G06F2217/82
摘要： The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.
摘要翻译：本公开提供了用于预测半导体可靠性的系统。在一个实施例中，用于预测半导体可靠性的方法包括接收半导体器件的劣化参数输入并使用劣化方程式根据劣化参数输入在短时间段内确定用于劣化的多个偏置相关斜率值。多个斜率值包括至少两个不同的斜率值，用于随着时间的推移而退化。系统累积多个斜率值，并且在长时间段内累积累积的斜率值，以确定半导体器件的应力效应。

3. 发明申请

US20120054709A1 Constructing Mapping Between Model Parameters and Electrical Parameters 有权
标题翻译：构建模型参数与电参数之间的映射
公开(公告)号：US20120054709A1
公开(公告)日：2012-03-01
申请号：US12871683
申请日：2010-08-30
申请人： Chen-Ming Tsai , Ke-Wei Su , Cheng Hsiao , Min-Chie Jeng , Jia-Lin Lo , Feng-Ling Hsiao , Yi-Shun Huang
发明人： Chen-Ming Tsai , Ke-Wei Su , Cheng Hsiao , Min-Chie Jeng , Jia-Lin Lo , Feng-Ling Hsiao , Yi-Shun Huang
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.
摘要翻译：一种方法包括确定模型参数与集成电路的电气参数之间的映射。模型参数被配置为由模拟工具使用。提供一组电参数，并且映射用于将该组参数映射到一组模型参数。

4. 发明授权

US08370774B2 Constructing mapping between model parameters and electrical parameters 有权
标题翻译：构建模型参数与电参数之间的映射
公开(公告)号：US08370774B2
公开(公告)日：2013-02-05
申请号：US12871683
申请日：2010-08-30
申请人： Chen-Ming Tsai , Ke-Wei Su , Cheng Hsiao , Min-Chie Jeng , Jia-Lin Lo , Feng-Ling Hsiao , Yi-Shun Huang
发明人： Chen-Ming Tsai , Ke-Wei Su , Cheng Hsiao , Min-Chie Jeng , Jia-Lin Lo , Feng-Ling Hsiao , Yi-Shun Huang
IPC分类号： G06F17/50 , G06F17/16 , G06F17/10
CPC分类号： G06F17/5009
摘要： A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.
摘要翻译：一种方法包括确定模型参数与集成电路的电气参数之间的映射。模型参数被配置为由模拟工具使用。提供一组电参数，并且映射用于将该组参数映射到一组模型参数。

5. 发明申请

US20120278050A1 Accelerated Generation of Circuit Parameter Distribution Using Monte Carlo Simulation 审中-公开
标题翻译：使用蒙特卡罗模拟加速生成电路参数分布
公开(公告)号：US20120278050A1
公开(公告)日：2012-11-01
申请号：US13097569
申请日：2011-04-29
申请人： Cheng Hsiao , Ke-Wei Su , Chung-Kai Lin , Min-Chie Jeng
发明人： Cheng Hsiao , Ke-Wei Su , Chung-Kai Lin , Min-Chie Jeng
IPC分类号： G06G7/62 , G06F17/10
CPC分类号： G06F17/5036
摘要： A method includes providing an integrated circuit device comprising a plurality of input parameters and an electrical parameter. A simulation is performed using a simulation model to simulate a plurality of data of the electrical parameter, wherein the plurality of data are generated through simulation from a first plurality of input parameter sets reflecting values of the plurality of input parameters, and wherein the plurality of data is distributed in a range. A first sub-range among the range is selected. All of the plurality of data falling into the first sub-range are selected, and are fitted with corresponding ones of the first input parameter sets to generate a first function, wherein the electrical parameter is expressed as the first function of the plurality of input parameters. The first function is different from functions in the simulation model.
摘要翻译：一种方法包括提供包括多个输入参数和电参数的集成电路装置。使用仿真模型进行模拟以模拟电参数的多个数据，其中通过反映多个输入参数的值的第一多个输入参数集的仿真来生成多个数据，并且其中，数据分布在一个范围内。选择范围内的第一个子范围。选择落入第一子范围的多个数据中的所有数据，并且与第一输入参数组中的相应的数据进行拟合以产生第一函数，其中，电参数表示为多个输入参数的第一函数。第一个功能与仿真模型中的功能不同。

6. 发明申请

US20130099352A1 STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING 有权
标题翻译：具有电容耦合的高K变压器的结构和方法
公开(公告)号：US20130099352A1
公开(公告)日：2013-04-25
申请号：US13280786
申请日：2011-10-25
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5222 , H01F17/0013 , H01L21/76805 , H01L21/76877 , H01L23/5225 , H01L23/5227 , H01L23/528 , H01L23/552 , H01L23/642 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有集成电路（IC）器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。

7. 发明授权

US07933747B2 Method and system for simulating dynamic behavior of a transistor 有权
标题翻译：用于模拟晶体管动态特性的方法和系统
公开(公告)号：US07933747B2
公开(公告)日：2011-04-26
申请号：US11935969
申请日：2007-11-06
申请人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
发明人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.
摘要翻译：公开了用于建模晶体管的动态行为的方法和系统。该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

8. 发明授权

US09923101B2 Semiconductor structure 有权
公开(公告)号：US09923101B2
公开(公告)日：2018-03-20
申请号：US13615503
申请日：2012-09-13
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
IPC分类号： H01L29/94 , H01L29/66 , H01L21/66 , H01L27/06 , H01L49/02 , H01L23/48 , H01L23/58
CPC分类号： H01L29/94 , H01L22/34 , H01L23/481 , H01L23/585 , H01L27/0629 , H01L28/60 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

9. 发明申请

US20140008773A1 Integrated Antenna Structure 有权
标题翻译：集成天线结构
公开(公告)号：US20140008773A1
公开(公告)日：2014-01-09
申请号：US13541937
申请日：2012-07-05
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L25/065 , H01L21/50
CPC分类号： H01Q1/38 , H01L23/66 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2223/6677 , H01L2924/0002 , H01Q1/2283 , H01Q1/40 , H01Q7/00 , H01L2924/00
摘要： Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure.
摘要翻译：一些实施例涉及包括被配置为无线传输信号的集成天线结构的半导体模块。集成天线结构具有下金属层和上金属层。下金属层设置在下模上并连接到接地端子。上金属层设置在上模上并连接到被配置为产生要无线传输的信号的信号发生器。上模具堆叠在下模上，并通过具有一个或多个微凸块的粘合层连接到下模。通过将粘合层连接在一起，下部和上部金属层彼此间隔开大间隔，从而提供了集成天线结构的良好性能。

10. 发明申请

US20120268229A1 Compact Vertical Inductors Extending in Vertical Planes 有权
标题翻译：紧凑的垂直电感器在垂直平面上延伸
公开(公告)号：US20120268229A1
公开(公告)日：2012-10-25
申请号：US13091440
申请日：2011-04-21
申请人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01F5/00 , H01F17/00
CPC分类号： H01F27/2804 , H01F17/0013 , H01F2017/002 , H01F2017/004 , H01F2027/2809 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
摘要翻译：器件包括衬底和衬底上的垂直电感器。垂直电感器包括由金属形成的多个部件，其中每个部件在与基板的主表面垂直的多个平面中的一个平面中延伸。金属线互连垂直电感器的多个部分中的相邻部分。

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