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1. 发明授权

US06798758B1 Method and apparatus for acquiring code synchronization in a CDMA communication system 失效
标题翻译：用于在CDMA通信系统中获取码同步的方法和装置
公开(公告)号：US06798758B1
公开(公告)日：2004-09-28
申请号：US09577596
申请日：2000-05-25
申请人： Ji-yong Chun , Hyoung-woon Park
发明人： Ji-yong Chun , Hyoung-woon Park
IPC分类号： H04B1707
CPC分类号： H04B1/708 , H04B1/709
摘要： Acquisition of initial code synchronization in a receiving system for a code division multiple access (CDMA) signal is realized by producing a complex digital signal having K components by sampling an analog signal derived from the received CDMA-modulated signal. Components of the complex digital signal are correlated with N code phases. The energies of these correlated values are examined, in parallel, to determine whether the ratio of the maximum energy within the block to the average energy in the block equals or exceeds a predetermined threshold. If so, this is a valid maximum, and the code synchronization is complete. If not, further components of the complex digital signal are correlated with another set of N code phases, and are examined in the same manner. Accordingly, reliable determination as to whether code synchronization has been achieved can be realized with minimal influence of channel distortion in a CDMA received signal.
摘要翻译：通过对从接收的CDMA调制信号中得到的模拟信号进行采样，产生具有K个分量的复数数字信号，来实现用于码分多址（CDMA）信号的接收系统中初始码同步的获取。复数字信号的分量与N个码相位相关。并行地检查这些相关值的能量，以确定块内的最大能量与块中的平均能量的比是否等于或超过预定阈值。如果是这样，这是有效的最大值，并且代码同步完成。如果不是，则复数字信号的其他分量与另一组N个码相位相关，并以相同的方式进行检查。因此，可以以CDMA接收信号中的信道失真的影响最小的方式来实现关于是否已经实现了码同步的可靠性。

2. 发明授权

US06480527B1 CDMA demodulating method and demodulator 有权
公开(公告)号：US06480527B1
公开(公告)日：2002-11-12
申请号：US09615718
申请日：2000-07-13
申请人： Eung-sun Kim , Ji-yong Chun
发明人： Eung-sun Kim , Ji-yong Chun
IPC分类号： H04B10148
CPC分类号： H04B1/711
摘要： A code division multiple access (CDMA) demodulating method and demodulator employing the demodulating method, the CDMA demodulating method including the steps of: (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers; (b) generating PN codes for each of the N paths and storing the PN codes in a predetermined second memory; (c) generating and sequentially-storing traffic walsh codes of one period, which correspond to a processing gain L, in a predetermined third memory; (d) multiplying a complex-conjugated value with one of the values stored in the first memory and one of the values stored in the second memory; (e) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories; (f) multiplying the resultant value of the step (d) with the traffic walsh codes of a corresponding path of data stored in the third memory; (g) cumulatively summing the resultant value of the step (f) L times for each of the N multi-paths to be processed, where L corresponds to the processing gain; (h) complex-conjugating the resultant value of the step (d) by cumulatively adding the resultant value of the step (d) X times for each of the N multi-path to be processed, where X corresponds to the data bit number of the walsh codes; (i) obtaining a number (N) of data by inputting the resultant value of the step (f) and the resultant value of the step (h) and multiplying the resultant value of the step (f) with the resultant value of the step (h); (j) sequentially-obtaining a number (N) of values by sequentially-inputting the number (N) of data obtained in the step (i) and taking only real values; (k) cumulatively summing the data obtained in the step (i) N times; and (l) deciding bit values based on logic values identified by identifying the logic values of the result of the step (k), whereby the complexity of the system and the power consumption may be reduced in terms of the number of necessary devices by allowing for suitable downloading of software and performing a demodulation operation in a processor.

3. 发明授权

US5659586A Digital timing recovery circuit including a loop filter having a varying band width 失效
标题翻译：数字定时恢复电路包括具有变化带宽的环路滤波器
公开(公告)号：US5659586A
公开(公告)日：1997-08-19
申请号：US366726
申请日：1994-12-30
申请人： Ji-yong Chun
发明人： Ji-yong Chun
IPC分类号： H04N5/06 , H03D13/00 , H03L7/091 , H03L7/093 , H03L7/107 , H03M7/34 , H04L7/02 , H04N5/14 , H04N5/935 , H04N19/00 , H04N19/102 , H04N19/117 , H04N19/134 , H04N19/196 , H04N19/80 , H04N19/82 , H04N19/85 , H04L7/00 , H03D3/24
CPC分类号： H04N5/935 , H03D13/003 , H03L7/091 , H03L7/107 , H03L7/093
摘要： A digital timing recovery circuit for recovering a sampling clock of a playback signal in digital equipment, provides a fast phase obtaining time, reduces a phase error so as to generate a stable sampling clock and a dead zone effect caused by performing a quantization using a limited number of bits in hardware, and includes an analog-to-digital converter, a phase error detector, a phase error comparator, a loop filter, a reference voltage generator, a digital-to-analog converter and a variable voltage oscillator, to thereby reduce the phase obtaining time by varying the bandwidth of the loop filter according to the phase error size detected by the phase error detector and reduce a sampling phase error caused by noise at a constant state.
摘要翻译：用于恢复数字设备中的重放信号的采样时钟的数字定时恢复电路提供快速相位获取时间，减少相位误差，从而产生稳定的采样时钟和通过使用有限的硬件中的位数，并且包括模数转换器，相位误差检测器，相位误差比较器，环路滤波器，参考电压发生器，数模转换器和可变电压振荡器，从而通过根据由相位误差检测器检测出的相位误差大小改变环路滤波器的带宽来减小相位获取时间，并减小由恒定状态引起的噪声引起的采样相位误差。

4. 发明授权

US6072828A Timing recovery apparatus and method using equalizer and apparatus for judging last data 失效
标题翻译：使用均衡器和装置判断最后数据的定时恢复装置和方法
公开(公告)号：US6072828A
公开(公告)日：2000-06-06
申请号：US990983
申请日：1997-12-15
申请人： Ji-yong Chun
发明人： Ji-yong Chun
IPC分类号： H03K9/00 , G11B20/14 , H03H7/30
CPC分类号： G11B20/1403
摘要： An apparatus for recovering timing using an equalizer of an E2PR4ML method and a method therefor and a last data judging apparatus. The timing recovery apparatus includes a sampling unit for sampling a reproduced signal and an equalizing unit for filtering the signal sampled by the sampling unit so as to output as a target signal E2PR4ML for detecting a timing error signal using the target signal output from the equalizing unit, phase synchronizing the detected timing error signal, and providing the phase-synchronized signal as a clock signal of the sampling unit. The timing recovery apparatus also includes a feedback filter using predetermined binary data as an input, an adder for adding the output signal of the feedback filter to the output signal of the equalizing unit and for outputting a new target signal, a data judging unit for detecting binary data on the basis of the new target signal and for generating quaternary data from the detected binary data, and a timing recovery unit for recovering timing by calculating the timing error of the sampling clock using the output signal of the data judging unit.
摘要翻译：一种使用E2PR4ML方法的均衡器及其方法来恢复定时的装置和最后的数据判断装置。定时恢复装置包括用于对再现信号进行采样的采样单元和用于对由采样单元采样的信号进行滤波的均衡单元，以便作为目标信号E2PR4ML输出，用于使用从均衡单元输出的目标信号来检测定时误差信号对所检测的定时误差信号进行相位同步，并且提供相位同步信号作为采样单元的时钟信号。定时恢复装置还包括使用预定的二进制数据作为输入的反馈滤波器，用于将反馈滤波器的输出信号与均衡单元的输出信号相加并用于输出新的目标信号的加法器，用于检测的数据判断单元基于新的目标信号的二进制数据和用于从所检测的二进制数据生成四进制数据的定时恢复单元，以及定时恢复单元，用于通过使用数据判断单元的输出信号计算采样时钟的定时误差来恢复定时。

5. 发明授权

US06888880B2 Apparatus for searching for a cell and method of acquiring code unique to each cell in an asynchronous wideband DS/CDMA receiver 失效
标题翻译：用于搜索小区的装置和获取异步宽带DS / CDMA接收机中的每个小区唯一的码的方法
公开(公告)号：US06888880B2
公开(公告)日：2005-05-03
申请号：US09758040
申请日：2001-01-11
申请人： Kang-min Lee , Ji-yong Chun
发明人： Kang-min Lee , Ji-yong Chun
IPC分类号： H04B7/26 , H04B1/707 , H04B1/7083 , H04B1/7087 , H04L7/00 , H04W48/16 , H04W64/00 , H04B1/69
CPC分类号： H04B1/70735 , H04B1/7083 , H04B1/7097
摘要： An apparatus for searching for a cell and a method of acquiring a code unique to each cell in an asynchronous wideband Direct-Sequence Code Division Multiple Access (DS/CDMA) receiver, wherein the cell searching apparatus searches for a cell based on a received asynchronous wideband DS/CDMA signal in a receiver, the apparatus including a code group identifying unit for estimating and compensating for a frequency error between the synchronous channel and an internally generated primary synchronization code, estimating and compensating for channel degradation which the synchronous channel has experienced, and performing correlation on the compensated synchronous channel and available secondary synchronization codes, thereby identifying the code group; and a scrambling code identifying unit for performing correlation on a plurality of scrambling codes belonging to the code group, thereby obtaining a scrambling code unique to each cell.
摘要翻译：一种用于搜索小区的装置和获取在异步宽带直接序列码分多址（DS / CDMA）接收机中的每个小区唯一的码的方法，其中小区搜索装置基于接收到的异步来搜索小区宽带DS / CDMA信号，所述装置包括用于估计和补偿同步信道与内部产生的主同步码之间的频率误差的码组识别单元，估计和补偿同步信道经历的信道劣化，并对补偿的同步信道和可用的次同步码进行相关，从而识别码组; 以及扰码识别单元，用于对属于该代码组的多个扰码执行相关，从而获得每个小区唯一的扰码。

6. 发明授权

US06842475B2 Apparatus for acquisition of asynchronous wideband DS/CDMA signal 有权
标题翻译：用于采集异步宽带DS / CDMA信号的装置
公开(公告)号：US06842475B2
公开(公告)日：2005-01-11
申请号：US09736195
申请日：2000-12-15
申请人： Yeon-kyoon Jeong , Kwang-bok Lee , Ji-yong Chun , Ki-ho Kim
发明人： Yeon-kyoon Jeong , Kwang-bok Lee , Ji-yong Chun , Ki-ho Kim
IPC分类号： H04B1/707 , H04B1/713 , H04B7/212 , H04B7/216
CPC分类号： H04B1/70756 , H04B1/70735 , H04B1/708 , H04B1/7093
摘要： An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are transmitted within one frame, and a group identification code indicating a code group, to which a base station belongs, are combined and transmitted with the common short code, includes: a long code masking correlation portion; a differentially coherent combining portion; a code group and frame timing acquisition portion; and a long code acquisition portion for acquiring the long code by correlating the long codes belonging to the acquired code group and the received long code, respectively.
摘要翻译：一种用于获取异步宽带直接序列/码分多址信号的装置，其从直接序列/码分多址控制信道信号中获取长码，其中公共短码和长码被发送在一帧内组合表示基站所属的代码组的组识别码与公共短码组合并发送，包括：长码屏蔽相关部分; 差分相干组合部分; 代码组和帧定时获取部分; 以及长码获取部分，用于通过分别属于所获取的代码组的长码与所接收的长码相关来获取长码。

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