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1. 发明授权

US07892918B2 Method of fabricating a semiconductor device including formation of contact holes 有权
标题翻译：制造包括形成接触孔的半导体器件的方法
公开(公告)号：US07892918B2
公开(公告)日：2011-02-22
申请号：US12170115
申请日：2008-07-09
申请人： Ji-Yoon Lee , Hyuck-Chai Jung
发明人： Ji-Yoon Lee , Hyuck-Chai Jung
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10885
摘要： A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.
摘要翻译：半导体器件中的布线结构包括形成在具有第一和第二接触区域的衬底上的第一绝缘层，以及延伸穿过第一绝缘层并且接触第一和第二接触区域的第一和第二焊盘。第一和第二焊盘高于第一绝缘层。在第一和第二焊盘之间的第一绝缘层上形成阻挡层图案，阻挡层图案高于第一和第二焊盘。在阻挡层图案和第一和第二焊盘上形成第二绝缘层。位线结构形成在第二绝缘层上，位线结构与第二焊盘电接触。在第二绝缘层和位线结构上形成第三绝缘层。插头延伸穿过第二绝缘层和第三绝缘层并接触第一焊盘。

2. 发明授权

US07816734B2 Field-effect transistor including localized halo ion regions, and semiconductor memory, memory card, and system including the same 有权
标题翻译：包括局部晕圈离子区域的场效应晶体管和半导体存储器，存储卡以及包括它们的系统
公开(公告)号：US07816734B2
公开(公告)日：2010-10-19
申请号：US12169137
申请日：2008-07-08
申请人： Hyuck-Chai Jung , June-Hee Lim
发明人： Hyuck-Chai Jung , June-Hee Lim
IPC分类号： H01L29/06 , H01L29/36
CPC分类号： H01L21/26586 , H01L21/823412 , H01L27/10873 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/66825 , H01L29/66833
摘要： A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.
摘要翻译：场效应晶体管包括可以优化HEIP特性和GIDL特性的局部卤素离子区域。场效应晶体管包括衬底，有源区，栅极结构和卤素离子区。有源区包括源极/漏极区域和形成在衬底中部分区域的沟道区域。栅结构与有源区电接触。卤素离子区域邻近衬底中的源极/漏极区域的两个端部局部形成。

3. 发明申请

US20080026524A1 SEMICONDUCTOR DEVICE HAVING A WELL STRUCTURE FOR IMPROVING SOFT ERROR RATE IMMUNITY AND LATCH-UP IMMUNITY AND A METHOD OF MAKING SUCH A DEVICE 审中-公开
标题翻译：具有用于改善软错误率免疫和锁定免疫的良好结构的半导体器件以及制造这种器件的方法
公开(公告)号：US20080026524A1
公开(公告)日：2008-01-31
申请号：US11868400
申请日：2007-10-05
申请人： Hyuck-Chai Jung
发明人： Hyuck-Chai Jung
IPC分类号： H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823892 , Y10S257/903
摘要： A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.
摘要翻译：具有提高的软错误率抗扰度和闭锁抗扰度的半导体器件及其形成方法。该器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱和第二导电类型的第二阱。在第二阱中形成包括第一导电类型的源极/漏极的第一导电类型的MOSFET，以及在第一阱中包括第二导电类型的源极/漏极的第二导电类型的MOSFET。第二导电类型的第三阱形成在第一导电型MOSFET的第一阱和漏极下方的区域。第一阱在第一阱和第三阱之间连接到半导体衬底。

4. 发明授权

US07294889B2 Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device 失效
标题翻译：具有用于提高软错误率抗扰度和闭锁抗扰度的良好结构的半导体器件和制造这种器件的方法
公开(公告)号：US07294889B2
公开(公告)日：2007-11-13
申请号：US10961927
申请日：2004-10-08
申请人： Hyuck-Chai Jung
发明人： Hyuck-Chai Jung
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L21/823892 , Y10S257/903
摘要： A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.
摘要翻译：具有提高的软错误率抗扰度和闭锁抗扰度的半导体器件及其形成方法。该器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱和第二导电类型的第二阱。在第二阱中形成包括第一导电类型的源极/漏极的第一导电类型的MOSFET，以及在第一阱中包括第二导电类型的源极/漏极的第二导电类型的MOSFET。第二导电类型的第三阱形成在第一导电型MOSFET的第一阱和漏极下方的区域。第一阱在第一阱和第三阱之间连接到半导体衬底。

5. 发明授权

US6084272A Electrostatic discharge protective circuit for semiconductor device 有权
标题翻译：半导体器件静电放电保护电路
公开(公告)号：US6084272A
公开(公告)日：2000-07-04
申请号：US263527
申请日：1999-03-05
申请人： Hyuck-Chai Jung
发明人： Hyuck-Chai Jung
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L27/01 , H01L27/12
CPC分类号： H01L27/0266 , H01L27/0288
摘要： An electrostatic discharge protective circuit including a semiconductor substrate, an input/output pad formed on the semiconductor substrate, a PMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, a first n+ diffusion layer formed in the semiconductor substrate and separated from the drain of the PMOS transistor at a predetermined interval while being connected to a Vcc terminal, a deep n+ diffusion layer formed between the drain of the PMOS transistor and the first n+ diffusion layer, an NMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, and second n+ diffusion layers formed around the NMOS transistor in the semiconductor substrate and connected to a Vss terminal.
摘要翻译：一种静电放电保护电路，包括半导体衬底，形成在所述半导体衬底上的输入/输出焊盘，形成在所述半导体衬底上并具有连接到所述输入/输出焊盘的漏极的PMOS晶体管，形成在所述半导体衬底中的第一n +扩散层衬底，并且在连接到Vcc端子处以预定间隔从PMOS晶体管的漏极分离，形成在PMOS晶体管的漏极和第一n +扩散层之间的深n +扩散层，形成在半导体衬底上的NMOS晶体管并且具有连接到输入/输出焊盘的漏极，以及形成在半导体衬底中的NMOS晶体管周围并连接到Vss端子的第二n +扩散层。

6. 发明申请

US20100093141A1 METHOD OF MANUFACTURING A TRANSISTOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造晶体管的方法和制造半导体器件的方法
公开(公告)号：US20100093141A1
公开(公告)日：2010-04-15
申请号：US12578291
申请日：2009-10-13
申请人： Hyuck-Chai Jung , Jun-Hee Lim
发明人： Hyuck-Chai Jung , Jun-Hee Lim
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L29/66575 , H01L21/26513 , H01L21/823456 , H01L27/0629 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L29/165 , H01L29/66628 , H01L29/7835
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.
摘要翻译：在制造晶体管的方法中，在基板上形成栅极结构。将第一杂质注入到衬底中以在与栅极结构相邻的衬底的上部形成杂质区。在杂质区上形成外延层。在衬底上形成具有部分暴露外延层的开口的绝缘层。将第二杂质注入由开口暴露的外延层的一部分。

7. 发明申请

US20080272430A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080272430A1
公开(公告)日：2008-11-06
申请号：US12111120
申请日：2008-04-28
申请人： Ki-Jae Hur , Jun-Hee Lim , Hyuck-Chai Jung
发明人： Ki-Jae Hur , Jun-Hee Lim , Hyuck-Chai Jung
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L29/66621
摘要： A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.
摘要翻译：半导体器件包括限定在衬底中的有源区，有源区具有在衬底的表面下方延伸的沟槽; 沿着沟槽的底表面和下侧壁设置的杂质区，其中杂质区的上部与衬底的表面和沟槽的上部间隔开; 栅极绝缘层，沿着沟槽的内表面设置; 以及设置在沟槽中的栅电极。

8. 发明授权

US6008115A Method for forming structure of wires for a semiconductor device 失效
标题翻译：用于形成用于半导体器件的导线结构的方法
公开(公告)号：US6008115A
公开(公告)日：1999-12-28
申请号：US997587
申请日：1997-12-23
申请人： Hyuck-Chai Jung
发明人： Hyuck-Chai Jung
IPC分类号： H01L27/108 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/00 , H01L21/425 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76877
摘要： Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures. The method includes the steps of: forming an interlayer insulating structure on the semiconductor device; forming contact holes through the interlayer insulating structure to expose the impurity regions; lining contact-hole-portions of the interlayer insulating layer with portions of a barrier layer, respectively, such that the portions of the barrier layer contact the impurity regions; forming conductive pads on the portions of the barrier layer such that remainders of the contact holes are filled; and forming a wire layer on each one of the conductive pads.
摘要翻译：公开了一种用于形成用于半导体器件的布线结构的方法，其中形成用于在单元区域中接触的焊盘以及单元宽高比非常高的芯区域和外围区域以及如此形成的导线的结构。半导体器件包括布置在单元区域和外围和/或芯区域中的半导体衬底，其中外围和/或芯区域在半导体衬底中形成良好，半导体衬底被布置成有源区域和场区域，半导体器件在场区域中也具有场绝缘层，在有源区域中的半导体衬底的部分上的多个栅极结构以及栅极结构之间的半导体衬底中的杂质区域。该方法包括以下步骤：在半导体器件上形成层间绝缘结构; 通过所述层间绝缘结构形成接触孔以暴露所述杂质区域; 分别将层间绝缘层的接触孔部分与阻挡层的部分层叠，使得阻挡层的部分与杂质区接触; 在所述阻挡层的所述部分上形成导电焊盘，使得所述接触孔的剩余部分被填充; 以及在每个导电焊盘上形成导线层。

9. 发明授权

US08848475B2 Fuse circuit, fuse array, semiconductor memory device and method of manufacturing semiconductor device 有权
标题翻译：保险丝电路，保险丝阵列，半导体存储器件及制造半导体器件的方法
公开(公告)号：US08848475B2
公开(公告)日：2014-09-30
申请号：US13219749
申请日：2011-08-29
申请人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
发明人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
IPC分类号： G11C17/18 , G11C17/16 , H01L27/10 , H01L23/525
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.
摘要翻译：熔丝电路包括程序单元和感测单元。程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。感测单元基于程序输出信号输出感测输出信号，并且感测输出信号指示程序单元是否被编程。程序单元包括反熔丝单元，选择晶体管，程序晶体管和感测晶体管。反熔丝单元包括至少两个并联连接的反熔丝元件，并分别以不同的编程电压电平分解。

10. 发明授权

US08836019B2 Recessed channel transistors, and semiconductor devices including a recessed channel transistor 有权
标题翻译：嵌入式沟道晶体管和包括凹陷沟道晶体管的半导体器件
公开(公告)号：US08836019B2
公开(公告)日：2014-09-16
申请号：US12591142
申请日：2009-11-10
申请人： Jun-Hee Lim , Hyuck-Chai Jung
发明人： Jun-Hee Lim , Hyuck-Chai Jung
IPC分类号： H01L29/66 , H01L27/108 , H01L21/265 , H01L49/02
CPC分类号： H01L29/66621 , H01L21/26586 , H01L27/10823 , H01L27/10876 , H01L28/90
摘要： A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.
摘要翻译：凹槽沟道晶体管，包括晶体管的半导体器件及其制造方法，凹陷沟道晶体管包括栅极结构，第二杂质区和第一杂质区。栅极结构可以形成在衬底上并填充凹部。包括第一杂质的第一杂质区可以形成在与栅极结构相邻的衬底的第一上部。包括第二杂质的第二杂质区可以形成在与栅极结构接触的基板的第二上部。第一杂质区可围绕第二杂质区。第一杂质具有与第二杂质不同的导电型。

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