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    • 6. 发明申请
    • INSTRUCTION AND LOGIC TO PROVIDE VECTOR BLEND AND PERMUTE FUNCTIONALITY
    • 指令和逻辑提供向量混合和绝对功能
    • US20140372727A1
    • 2014-12-18
    • US13977734
    • 2011-12-23
    • Robert ValentineBret L. TollJesus CorbalJeff G. WiedemeierSridhar Samudrala
    • Robert ValentineBret L. TollJesus CorbalJeff G. WiedemeierSridhar Samudrala
    • G06F9/30G06F9/38
    • G06F9/30036G06F9/3001G06F9/30018G06F9/30032G06F9/3887
    • Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
    • 提供向量混合和置换功能,响应于指令:包括存储向量元素的字段的目的地向量寄存器,第一向量寄存器,向量元素大小,第二向量寄存器和第三操作数。 指数从第二个寄存器中的字段读取。 每个索引具有第一选择器部分和第二选择器部分。 对应的未屏蔽向量元素被存储到目的地寄存器的字段,其中响应于具有第一值的相应第一选择器部分的每个向量元素从第一寄存器的对应数据字段被复制到中间向量,并且响应于 具有第二值的相应的第一选择器部分从第三操作数的相应数据字段复制到中间向量。 然后,由对应的第二选择器部分索引的中间向量中的数据字段替换目的地的未屏蔽的数据字段。
    • 8. 发明申请
    • DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
    • 双重圆形组合浮点数乘法和加法
    • US20140006467A1
    • 2014-01-02
    • US13539198
    • 2012-06-29
    • Sridhar SamudralaGrigorios MagklisMarc LuponDavid R. Ditzel
    • Sridhar SamudralaGrigorios MagklisMarc LuponDavid R. Ditzel
    • G06F7/44G06F7/42
    • G06F7/4876G06F7/483G06F7/485G06F7/4991G06F7/49915G06F7/5443G06F2207/4802
    • Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
    • 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法,装置,指令和逻辑。 实施例包括检测浮点(FP)乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作,包括对FP乘法的结果进行舍入,随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行,所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测,第一和第二FP加法器来添加第三操作数加法尾数, 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。