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1. 发明授权

US07184487B2 Receiver with chopper stabilization and method thereof 有权
标题翻译：具有斩波稳定的接收机及其方法
公开(公告)号：US07184487B2
公开(公告)日：2007-02-27
申请号：US11019750
申请日：2004-12-21
申请人： Jerry T. Bolton, Jr. , Joseph P. Heck
发明人： Jerry T. Bolton, Jr. , Joseph P. Heck
IPC分类号： H04B15/00
CPC分类号： H03D7/161 , H03D7/18 , H04B1/10 , H04B1/28
摘要： A receiver (202) has a down-conversion receiver (304) for transforming a signal (201) from a first operating frequency to a second operating frequency that is lower than the first operating frequency, and a receiver filter (308) with chopper stabilization for filtering unwanted portions of the signal (306) at the second operating frequency and for generating a final filtered signal (203) at the second operating frequency.
摘要翻译：接收器（202）具有用于将信号（201）从第一工作频率变换到低于第一工作频率的第二工作频率的下变频接收器（304），以及具有斩波稳定的接收机滤波器（308）用于在第二操作频率处滤除信号（306）的不需要的部分并且用于在第二操作频率产生最终滤波信号（203）。

2. 发明授权

US06490326B1 Method and apparatus to correct for in-phase and quadrature-phase gain imbalance in communication circuitry 有权
标题翻译：校正通信电路中的同相和正交相位增益不平衡的方法和装置
公开(公告)号：US06490326B1
公开(公告)日：2002-12-03
申请号：US09366757
申请日：1999-08-04
申请人： Babak Bastani , Edwin E. Bautista , Joseph P. Heck
发明人： Babak Bastani , Edwin E. Bautista , Joseph P. Heck
IPC分类号： H04L2506
CPC分类号： H04L27/22 , H04L27/0014 , H04L2027/0024
摘要： Communication apparatus (100) corrects for amplitude imbalance caused by differences in circuitry that process in-phase and quadrature signals. The in-phase and quadrature signals are alternately routed in rapid succession through first and second parallel processing circuits or signal paths (140, 150) to cancel imbalances between the signal paths. Switches (132, 134) are employed at inputs to and outputs from corresponding portions of both signal paths, and these switches (132, 134) are synchronously operated in response to a control signal to interchange signals on the signal paths.
摘要翻译：通信装置（100）校正由处理同相和正交信号的电路的差异引起的幅度不平衡。同相和正交信号通过第一和第二并行处理电路或信号路径（140,150）以快速连续的方式交替路由，以消除信号路径之间的不平衡。开关（132,134）在两个信号路径的相应部分的输入端和输出端被使用，并且这些开关（132,134）响应于控制信号被同步操作以在信号路径上交换信号。

3. 发明授权

US5446761A Decoder circuit for phase modulated signals 失效
标题翻译：用于相位调制信号的解码电路
公开(公告)号：US5446761A
公开(公告)日：1995-08-29
申请号：US74525
申请日：1993-06-11
申请人： Manbir Nag , Joseph P. Heck
发明人： Manbir Nag , Joseph P. Heck
IPC分类号： H03D3/00 , H03G3/30 , H03K9/06
CPC分类号： H03G3/3036 , H03D3/007 , H03D2200/0019 , H03D2200/0027 , H03D2200/0043 , H03D2200/0047
摘要： A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31. The gain control circuit (28) receives the control signal (31) and the amplitude varying signal (15) and outputs an amplitude compensated signal (38).
摘要翻译：一种解码器电路（21）以及通过消除相位调制信号上不期望的调幅影响来提供幅度补偿信号的方法。解调器方法是通过对相位调制信号的接收的同相接收信号分量（10）和正交接收信号分量（12）进行解调，并将幅度变化信号（15）输出到输出幅度补偿的前馈自动增益控制电路信号（38）。前馈自动增益控制电路包括检测器电路（16），偏移偏置电路（32），差分电路（30）和增益控制电路（28）。检测器电路（16）输出表示同相接收信号（10）和正交接收信号（12）的振幅的DC信号（17）。偏移电路（32）向DC信号（17）提供恒定电流偏置（29），从而产生控制信号31.增益控制电路（28）接收控制信号（31）和幅度变化信号（15 ）并输出振幅补偿信号（38）。

4. 发明授权

US4714899A Frequency synthesizer 失效
标题翻译：频率合成器
公开(公告)号：US4714899A
公开(公告)日：1987-12-22
申请号：US913426
申请日：1986-09-30
申请人： Gary Kurtzman , Joseph P. Heck , Kenneth A. Hansen , Ralph Enderby , Bronis Vidugiris
发明人： Gary Kurtzman , Joseph P. Heck , Kenneth A. Hansen , Ralph Enderby , Bronis Vidugiris
IPC分类号： H03C3/09 , H03L7/193 , H03L7/06 , H03L7/10
CPC分类号： H03C3/0991 , H03C3/0925 , H03C3/0933 , H03L7/193
摘要： A programmable frequency synthesizer is disclosed having most components implemented on a single large scale integration (LSI) chip, which facilitates rapid frequency acquisition. Provision is made by the present invention to configure the frequency synthesizer for use in either a receiver or a transmitter. In the transmitter mode, modulation cancelling allows modulation down to approximate DC. A serial programming protocol is provided to program the frequency synthesizer.
摘要翻译：公开了一种可编程频率合成器，其中大多数组件实现在单个大规模集成（LSI）芯片上，这有助于快速频率采集。本发明提出了配置用于接收机或发射机的频率合成器。在发射机模式下，调制消除允许调制到近似直流。提供串行编程协议来对频率合成器进行编程。

5. 发明授权

US08428544B2 Heterodyne commutating mixer apparatus 有权
标题翻译：异步换向混合装置
公开(公告)号：US08428544B2
公开(公告)日：2013-04-23
申请号：US13191748
申请日：2011-07-27
申请人： Joseph P. Heck , Stephen L. Kuffner
发明人： Joseph P. Heck , Stephen L. Kuffner
IPC分类号： H04B1/26
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165
摘要： Heterodyne commutating apparatuses and methods for creating the heterodyne commutating apparatuses are disclosed. The heterodyne commutating mixer includes a plurality of switches for transferring a radio frequency input signal sequentially during a plurality of local oscillator period timeslots to a plurality of output capacitors. The heterodyne commutating mixer also includes a plurality of inductors added across differential in-phase output terminals and quadrature output terminals. Values of inductance and capacitance are set to achieve resonance at an output intermediate frequency.
摘要翻译：公开了用于产生外差整流装置的异步换向装置和方法。外差整流混频器包括多个开关，用于在多个本地振荡器周期时隙期间将射频输入信号顺序地传送到多个输出电容器。外差整流混频器还包括跨差分同相输出端子和正交输出端子加上的多个电感器。电感和电容值被设置为在输出中频下实现谐振。

6. 再颁专利

USRE33157E Null initiated method and system for monitoring a priority channel 失效
标题翻译：零启动的方法和监控优先级通道的系统
公开(公告)号：USRE33157E
公开(公告)日：1990-01-30
申请号：US160216
申请日：1988-02-24
申请人： Joseph P. Heck
发明人： Joseph P. Heck
IPC分类号： H03J7/18
CPC分类号： H03J7/18
摘要： A null initiated priority channel monitoring system provides enhanced nonpriority signal intelligibility and/or enhanced priority channel sensitivity during sample times. The priority channel or channels are monitored during nulls in the received nonpriority signal. The system can have a minimum time period between priority channel monitoring periods to avoid substantially continuous priority channel monitoring. The system can also have a maximum time period between priority channel monitoring or sampling periods to avoid missing any priority channel signal.

7. 发明授权

US4755774A Two-port synthesizer modulation system employing an improved reference phase modulator 失效
标题翻译：采用改进的参考相位调制器的双端口合成器调制系统
公开(公告)号：US4755774A
公开(公告)日：1988-07-05
申请号：US913625
申请日：1986-09-30
申请人： Joseph P. Heck
发明人： Joseph P. Heck
IPC分类号： H03C3/09 , H03L7/081
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/0958 , H03C3/0966 , H03L7/081 , H03C2200/0054
摘要： An improved frequency modulator apparatus for use in phase-locked loop (PLL) frequency synthesizers is disclosed which makes possible high deviation, low distortion, FM signals for a wide range of modulating signals, such as digital data or low frequency tone modulation. In a first embodiment having the improved frequency modulator, this apparatus advantageously injects the modulation signal into two ports, one at the VCO and the other provided in an unmodulated reference source signal chain. By properly balancing the levels into each of these two ports, a cancellation effect occurs which nulls the modulation signal at the output of the phase detector. In a second embodiment, the improved frequency modulator is incorporated in a PLL frequency synthesizer with an offset mixer to achieve relatively wide percentage deviation at a low frequency RF carrier. In a third embodiment, the improved frequency modulator is incorporated in a PLL synthesizer in its feedback loop so as to cancel the modulation components before they reach the phase detector. Thus, in the first two embodiments, the added phase modulator is inserted in the reference source signal path to the phase detector, while in the alternate third embodiment, the phase modulator is inserted into the feedback path and includes a phase inverter stage to correct for the inherent modulation polarity reversal.
摘要翻译：公开了一种用于锁相环（PLL）频率合成器的改进的频率调制器装置，其可以用于宽范围的调制信号（例如数字数据或低频调制调制）的高偏差，低失真的FM信号。在具有改进的频率调制器的第一实施例中，该装置有利地将调制信号注入到两个端口中，一个在VCO处，另一个设置在未调制的参考源信号链中。通过适当地平衡这两个端口中的每个端口的电平，发生消除效应，使相位检测器的输出处的调制信号无效。在第二实施例中，改进的频率调制器被并入具有偏移混频器的PLL频率合成器中，以在低频RF载波处实现相对较宽的百分比偏差。在第三实施例中，改进的频率调制器被并入其PLL反馈回路中的PLL合成器中，以便在它们到达相位检测器之前消除调制分量。因此，在前两个实施例中，将相加的相位调制器插入到相位检测器的参考源信号路径中，而在替代的第三实施例中，相位调制器被插入到反馈路径中，并且包括相位逆变器级，以校正固有的调制极性反转。

8. 发明授权

US4748425A VCO range shift and modulation device 失效
标题翻译： VCO范围移位和调制装置
公开(公告)号：US4748425A
公开(公告)日：1988-05-31
申请号：US16024
申请日：1987-02-18
申请人： Joseph P. Heck
发明人： Joseph P. Heck
IPC分类号： H03C3/09 , H03L7/093 , H03C3/22
CPC分类号： H03C3/0958 , H03L7/093
摘要： A modulation and range shift device for use with a PLL frequency synthesizer VCO. The modulation signal is provided to the negative side of the tuning varactor (16) of the VCO (14). In addition, variable voltages can be applied to the negative side of the tuning varactor (16) to achieve range shift as desired. Component variations in the modulation section (18) need not be varied to accommodate changes in the loop filter (12 and 13) of the PLL circuit.
摘要翻译：一种与PLL频率合成器VCO一起使用的调制和范围移位装置。调制信号被提供给VCO（14）的调谐变容二极管（16）的负侧。此外，可变电压可以施加到调谐变容二极管（16）的负侧以实现期望的范围偏移。调制部分（18）中的分量变化不需要改变以适应PLL电路的环路滤波器（12和13）的变化。

9. 发明授权

US4653117A Dual conversion FM receiver using phase locked direct conversion IF 失效
标题翻译：双转换FM接收机采用锁相直接转换IF
公开(公告)号：US4653117A
公开(公告)日：1987-03-24
申请号：US799387
申请日：1985-11-18
申请人： Joseph P. Heck
发明人： Joseph P. Heck
IPC分类号： H03D3/00 , H03D3/22 , H03D3/24 , H03D7/16 , H04B1/16 , H04B1/30
CPC分类号： H04B1/18 , H03D3/007 , H03D3/242 , H03D7/166 , H03D3/22 , H03D7/161
摘要： A receiver for frequency modulated signals, having down-conversion to a baseband, zero intermediate frequency for selectivity, followed by up-conversion to a non-zero IF for amplification, limiting, and demodulation.A phase-lock loop locks the frequency of the down-conversion source to the center frequency of the signal coupled to the baseband IF, converting the signal to precisely zero frequency. This avoids the beat note often found in direct conversion systems. The phase-lock loop additionally provides inherent demodulation of the FM signal.The received FM signal is coupled to the baseband IF through a radio frequency amplifier for improved sensitivity and local oscillator isolation, or through a first IF comprising a mixer, local oscillator, filter, and amplifier.
摘要翻译：用于频率调制信号的接收机，具有下变频到基带，零中频以进行选择性，随后上变频到非零IF用于放大，限幅和解调。锁相环锁定下变频源的频率到耦合到基带IF的信号的中心频率，将信号转换为精确的零频率。这避免了在直接转换系统中经常发现的节拍。锁相环还提供FM信号的固有解调。所接收的FM信号通过射频放大器耦合到基带IF，以提高灵敏度和本地振荡器隔离，或通过包括混频器，本地振荡器，滤波器和放大器的第一IF。

10. 发明授权

US07236763B2 Method and apparatus providing improved mixer performance for radio receivers 失效
标题翻译：为无线电接收机提供改进的混频器性能的方法和装置
公开(公告)号：US07236763B2
公开(公告)日：2007-06-26
申请号：US10860837
申请日：2004-06-04
申请人： Joseph P. Heck
发明人： Joseph P. Heck
IPC分类号： H04B1/26
CPC分类号： H03D7/163 , H03D7/166
摘要： A mixer circuit (50) includes a first switching mixer (20A) with a first desired signal input (RF+ and RF−), a first switching signal input (LO+& LO−), and a first output (IF+ and IF−), a second switching mixer (20B), and a third switching mixer (20C) with corresponding desired signal inputs, switching signal inputs, and outputs. An overall input signal to the mixer circuit is fed to an input port (56) of the first switching mixer, an output from an output port (57) of the first switching mixer is fed to an input port (58) of the second switching mixer, the output from an output port (59) of the second switching mixer is fed to an input port (60) of the third switching mixer, and an overall output of the mixer circuit can be an output from an output port (62) of the third switching mixer.
摘要翻译：混频器电路（50）包括具有第一期望信号输入（RF +和RF-）的第一开关混频器（20A），第一开关信号输入（LO + LO-）和第一输出（IF +和IF- ），第二开关混频器（20B）和具有对应的期望信号输入，开关信号输入和输出的第三开关混频器（20C）。向混频器电路的总输入信号被馈送到第一开关混频器的输入端口（56），来自第一开关混频器的输出端口（57）的输出被馈送到第二开关的输入端口（58）来自第二开关混频器的输出端口（59）的输出被馈送到第三开关混频器的输入端口（60），并且混频器电路的总输出可以是输出端口（62）的输出端，的第三个开关混频器。

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