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1. 发明授权

US06771264B1 Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor 有权
标题翻译：在延迟着色图形处理器中执行切线空间照明和凹凸贴图的方法和装置
公开(公告)号：US06771264B1
公开(公告)日：2004-08-03
申请号：US09213990
申请日：1999-12-17
申请人： Jerome F. Duluk , Stephen L. Dodgen , Joseph P. Bratt , Matthew Papakipos , Nathan Tuck , Richard E. Hessel
发明人： Jerome F. Duluk , Stephen L. Dodgen , Joseph P. Bratt , Matthew Papakipos , Nathan Tuck , Richard E. Hessel
IPC分类号： G06T1560
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (vs, vt, n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor. The Phong shader performs all lighting computations in eye space, which requires it first to transform bump data from tangent space to eye space. In one embodiment the Phong hardware does this by multiplying a matrix M whose columns comprise eye space basis vectors (bs, bt, n) derived from the surface basis vectors (vs, vt, n) and the vector Tb of bump map data. The eye space basis vectors are derived by the DSGP preprocessor so that the multiplication (M×Tb) gives the perturbed surface normal N′ in eye space, reflecting the bump effects. The perturbed surface normal N′ is subsequently used in the lighting computations.
摘要翻译：用于在延迟着色图形处理器（DSGP）中执行切线空间照明的系统和方法包括预处理数据的DSGP的块和仅在所有片段被预处理之后才执行的Phong着色器。预处理器块接收以各种格式指定的纹理贴图，并将这些纹理贴图转换为普通格式供Phong着色器使用。预处理器块为Phong着色器提供了内插表面基向量（vs，vt，n），一个向量Tb，它在切向/对象空间中表示纹理贴图中的纹理/凹凸数据，光数据，材料数据，眼睛坐标等 Phong着色器使用的信息执行照明和凹凸贴图计算。为需要计算照明效果的每个片段提供来自预处理器的数据。 Phong着色器使用预处理器提供的信息计算片段的颜色。 Phong着色器执行眼睛空间中的所有照明计算，这需要它首先将凹凸数据从切线空间转换为眼睛空间。在一个实施例中，Phong硬件通过乘以其列包括从表面基矢量（vs，vt，n）导出的凹凸贴图数据的矢量Tb的基准矢量（bs，bt，n）的矩阵M来实现。通过DSGP预处理器导出眼空间基矢量，使得乘法（MxTb）给出了眼空间中的扰动表面法线N'，反映了碰撞效应。扰动表面法线N'随后用于照明计算。

2. 发明授权

US06597363B1 Graphics processor with deferred shading 有权
标题翻译：具有延迟着色的图形处理器
公开(公告)号：US06597363B1
公开(公告)日：2003-07-22
申请号：US09378637
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.
摘要翻译：描述了包括许多子结构的图形处理器和方法，包括专用子系统，子处理器，设备，架构和相应的过程。本发明的实施例可以包括延迟着色，出血帧缓冲器和多级隐藏表面去除处理以及其他结构和/或程序中的一个或多个。本发明的实施例被设计为提供具有Phong着色，子像素抗锯齿，纹理和凹凸映射的高性能3D图形。

3. 发明授权

US06268875B1 Deferred shading graphics pipeline processor 有权
标题翻译：延迟着色图形流水线处理器
公开(公告)号：US06268875B1
公开(公告)日：2001-07-31
申请号：US09632293
申请日：2000-08-04
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.
摘要翻译：三维计算机图形系统和方法，更具体地涉及三维图形处理器的结构和方法，并具有其他增强的图形处理特征。在一个实施例中，图形处理器是包括AGP接口，命令提取和解码（2000），几何单元（3000），模式提取（4000）和多边形存储器（5000）的延迟着色图形处理器（DSGP）分类单元（6000）和分类存储器（7000），设置单元（8000），剔除单元（9000），模式注入（10000），片段单元（11000），纹理（12000）和纹理存储器）阴影（14000），像素单元（15000），耦合到帧缓冲器（17000）的后端单元（1600）。其他实施例不需要包括所有这些功能单元，并且这些单元的结构和方法适用于其他计算过程和系统以及延迟和非延迟着色图形处理器。

4. 发明授权

US07167181B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07167181B2
公开(公告)日：2007-01-23
申请号：US10458493
申请日：2003-06-09
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/40 , G09G5/00
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺的帧缓冲器和多个阶段隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

5. 发明授权

US06229553B1 Deferred shading graphics pipeline processor 有权
标题翻译：延迟着色图形流水线处理器
公开(公告)号：US06229553B1
公开(公告)日：2001-05-08
申请号：US09378299
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.
摘要翻译：三维计算机图形系统和方法，更具体地涉及三维图形处理器的结构和方法，并具有其他增强的图形处理特征。在一个实施例中，图形处理器是包括AGP接口，命令提取解码（2000），几何单元（3000），模式提取（4000）和多边形存储器（5000）的延迟着色图形处理器（DSGP），分类单元（6000）和分类存储器（7000），设置单元（8000），剔除单元（9000），模式注入（10000），片段单元（11000），纹理（12000）和纹理存储器（13000）（14000），像素单元（15000），耦合到帧缓冲器（17000）的后端单元（1600）。其他实施例不需要包括所有这些功能单元，并且这些单元的结构和方法适用于其他计算过程和系统以及延迟和非延迟着色图形处理器。

6. 发明授权

US07808503B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07808503B2
公开(公告)日：2010-10-05
申请号：US11613093
申请日：2006-12-19
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/00 , G06T15/10
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

7. 发明授权

US06717576B1 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US06717576B1
公开(公告)日：2004-04-06
申请号：US09377503
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

8. 发明授权

US06525737B1 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06525737B1
公开(公告)日：2003-02-25
申请号：US09378439
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元从多边形存储器接收输入并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

9. 发明授权

US06693639B2 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06693639B2
公开(公告)日：2004-02-17
申请号：US10290414
申请日：2002-11-07
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元接收来自多边形存储器的输入，并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

10. 发明授权

US09332239B2 Systems and methods for RGB image processing 有权
标题翻译： RGB图像处理系统和方法
公开(公告)号：US09332239B2
公开(公告)日：2016-05-03
申请号：US13484814
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
IPC分类号： G06K9/00 , H04N9/64 , G06T5/00 , G06T1/20
CPC分类号： H04N9/646 , G06T1/20 , G06T3/4015 , G06T5/002 , G06T5/009 , G06T5/20 , G06T2207/10024 , H04N5/365 , H04N9/045 , H04N9/735
摘要： Systems and methods for processing image data in RGB format are provided. In one example, an electronic device includes memory to store image data in raw or RGB format, or both, and an RGB image processing pipeline to process the image data. Specifically, the RGB image processing pipeline may process the image data regardless of whether the image data is of raw or RGB format. The RGB image processing pipeline may include receiving logic to receive the image data in raw or RGB format and demosaicing logic to, when the receiving logic receives the image data in raw format, convert the image data into RGB format. The logic may include local tone mapping logic configured to apply spatially varying tone curves to the image data, a color correction matrix configured to correct color in the image data, and gamma logic configured to transform the image data into gamma space.
摘要翻译：提供了以RGB格式处理图像数据的系统和方法。在一个示例中，电子设备包括用于以原始或RGB格式或两者存储图像数据的存储器和用于处理图像数据的RGB图像处理流水线。具体而言，RGB图像处理流水线可以处理图像数据，而不管图像数据是原始还是RGB格式。 RGB图像处理流水线可以包括接收逻辑以接收原始或RGB格式的图像数据和去马赛克逻辑，当接收逻辑以原始格式接收图像数据时，将图像数据转换为RGB格式。逻辑可以包括被配置为将空间变化的色调曲线应用于图像数据的本地色调映射逻辑，配置为校正图像数据中的颜色的色彩校正矩阵，以及被配置为将图像数据变换为伽马空间的伽马逻辑。

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