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1. 发明授权

US5305446A Processing devices with improved addressing capabilities, systems and methods 失效
标题翻译：具有改进的寻址能力，系统和方法的处理设备
公开(公告)号：US5305446A
公开(公告)日：1994-04-19
申请号：US589968
申请日：1990-09-28
申请人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
发明人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
IPC分类号： G06F9/30 , G06F9/32 , G06F9/345 , G06F9/355 , G06F9/38 , G06F12/02
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。还包括用于存储表示存储电路地址的初始地址字的地址寄存器。连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器以产生存储电路地址。还公开了其他装置，系统和方法。

2. 发明授权

US06625719B2 Processing devices with improved addressing capabilities systems and methods 失效
标题翻译：具有改进的寻址能力的处理设备系统和方法
公开(公告)号：US06625719B2
公开(公告)日：2003-09-23
申请号：US10172590
申请日：2002-06-14
申请人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
发明人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
IPC分类号： G06F1200
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。还包括用于存储表示存储电路地址的初始地址字的地址寄存器。连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器以产生存储电路地址。还公开了其他装置，系统和方法。

3. 发明授权

US06411984B1 Processor integrated circuit 失效
标题翻译：处理器集成电路
公开(公告)号：US06411984B1
公开(公告)日：2002-06-25
申请号：US09071718
申请日：1998-05-01
申请人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
发明人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
IPC分类号： G06F1300
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。还包括用于存储表示存储电路地址的初始地址字的地址寄存器。连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器以产生存储电路地址。还公开了其他装置，系统和方法。

4. 发明授权

US5751991A Processing devices with improved addressing capabilities, systems and methods 失效
标题翻译：具有改进的寻址能力，系统和方法的处理设备
公开(公告)号：US5751991A
公开(公告)日：1998-05-12
申请号：US420458
申请日：1995-04-10
申请人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
发明人： Jerald G. Leach , Laurence R. Simar , Alan L. Davis , Reid E. Tatge
IPC分类号： G06F9/30 , G06F9/32 , G06F9/345 , G06F9/355 , G06F9/38 , G06F9/34
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。还包括用于存储表示存储电路地址的初始地址字的地址寄存器。连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器以产生存储电路地址。还公开了其他装置，系统和方法。

5. 发明授权

US5809309A Processing devices with look-ahead instruction systems and methods 失效
标题翻译：具有先行指示系统和方法的处理设备
公开(公告)号：US5809309A
公开(公告)日：1998-09-15
申请号：US712244
申请日：1996-09-11
申请人： Jerald G. Leach , Laurence R. Simar
发明人： Jerald G. Leach , Laurence R. Simar
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/46
CPC分类号： G06F9/4812 , G06F9/30145 , G06F9/30167 , G06F9/3877
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address. A interrupt handler unit, connected to the instruction decode and control unit and the memory, having a hold register operative to store the program register, responsive to the control signals from the instruction decode and control unit to generate an intermediate address to access an interrupt counter from the memory, is operative to store the program register into the hold register and replace the program register with the interrupt counter wherein the interrupt counter corresponds to an address for accessing an interrupt instruction to execute an interrupt routine stored in the memory. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，连接到存储器的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。连接到具有用于保存程序指令的指令寄存器的存储器的指令解码和控制单元可操作以对提供控制信号的程序指令进行解码，以控制数据处理设备的操作，并响应于具有中断指令的指令代码。连接到存储器的程序定序器电路具有用于保存与程序地址相对应的程序计数器的程序寄存器，用于使用程序寄存器访问存储器，以获得与程序地址相对应的程序指令。连接到指令解码和控制单元和存储器的中断处理单元响应于来自指令解码和控制单元的控制信号产生中间地址以访问中断计数器，具有可操作以存储程序寄存器的保持寄存器从存储器开始，将程序寄存器存储到保持寄存器中，并且用中断计数器替换程序寄存器，其中中断计数器对应于访问中断指令的地址，以执行存储在存储器中的中断程序。还公开了其他装置，系统和方法。

6. 发明授权

US5535348A Block instruction 失效
标题翻译：块指令
公开(公告)号：US5535348A
公开(公告)日：1996-07-09
申请号：US420932
申请日：1995-04-12
申请人： Jerald G. Leach , Joseph A. Coomes , Steve P. Marshall , Laurence R. Simar
发明人： Jerald G. Leach , Joseph A. Coomes , Steve P. Marshall , Laurence R. Simar
IPC分类号： G06F9/312 , G06F9/34 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。还公开了其他装置，系统和方法。

7. 发明授权

US5390304A Method and apparatus for processing block instructions in a data processor 失效
标题翻译：用于访问多个存储器件的方法和装置。
公开(公告)号：US5390304A
公开(公告)日：1995-02-14
申请号：US590372
申请日：1990-09-28
申请人： Jerald G. Leach , Laurence R. Simar
发明人： Jerald G. Leach , Laurence R. Simar
IPC分类号： G06F9/312 , G06F9/34 , G06F9/38 , G06F12/06
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。还公开了其他装置，系统和方法。

8. 发明授权

US5410652A Data communication control by arbitrating for a data transfer control token with facilities for halting a data transfer by maintaining possession of the token 失效
标题翻译：数据通信控制通过仲裁数据传输控制令牌与通过维持拥有令牌来停止数据传输的设施
公开(公告)号：US5410652A
公开(公告)日：1995-04-25
申请号：US265977
申请日：1994-06-27
申请人： Jerald G. Leach , Laurence R. Simar
发明人： Jerald G. Leach , Laurence R. Simar
IPC分类号： G06F13/37 , G06F13/14
CPC分类号： G06F13/37
摘要： A data processing device for use with another data processing circuit sending data and requests for service thereto. The data processing device includes a processor circuit, a communication port connected to said processor circuit, having a data buffer including a plurality of registers comprising a first-in-first-out (FIFO) circuit and a plurality of external terminals, the communication port operative to communicate with the external terminals. Further included is a FIFO control unit, connected to the registers of the FIFO circuit, operative to provide FIFO control signals for data transfers between the communication port and the FIFO circuit. A port arbitration unit, connected to the FIFO control unit, has a port arbitration register and is operative to exchange port control signals for arbitrating port control between requests from the processor circuit and the external terminals. Other devices, systems and methods are also disclosed.
摘要翻译：一种数据处理装置，用于与另一数据处理电路一起发送数据和请求服务。数据处理装置包括处理器电路，连接到所述处理器电路的通信端口，具有包括多个寄存器的数据缓冲器，所述寄存器包括先进先出（FIFO）电路和多个外部端子，所述通信端口可操作地与外部终端通信。还包括FIFO控制单元，连接到FIFO电路的寄存器，可操作以提供用于在通信端口和FIFO电路之间进行数据传输的FIFO控制信号。连接到FIFO控制单元的端口仲裁单元具有端口仲裁寄存器，并用于交换端口控制信号，用于在来自处理器电路和外部端子的请求之间仲裁端口控制。还公开了其他装置，系统和方法。

9. 发明授权

US5784700A Memory interface with address shift for different memory types 失效
标题翻译：具有不同存储器类型的地址移位的存储器接口
公开(公告)号：US5784700A
公开(公告)日：1998-07-21
申请号：US641820
申请日：1996-05-02
申请人： Chein C. Chen , John C. Cooper , David E. Francis , Joseph A. Coomes , Jerald G. Leach
发明人： Chein C. Chen , John C. Cooper , David E. Francis , Joseph A. Coomes , Jerald G. Leach
IPC分类号： G06F12/02 , G06F12/06 , G06F13/40
CPC分类号： G06F13/4018 , G06F12/0215 , G06F12/0623
摘要： A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.
摘要翻译：一种能够将微处理器耦合到微处理器外部的存储器的存储器接口单元，其中存储器可以是宽度不同的至少两种类型，并且其中存储在这种存储器中的数据可以具有不同的尺寸，并且其中存储器可以是形成在部分。本发明利用了用于控制至少两个选通信号线的装置以及可编程地移位存储器地址线的装置，以便适应存储器宽度和数据大小的各种组合。

10. 发明授权

US5184032A Glitch reduction in integrated circuits, systems and methods 失效
标题翻译：集成电路，系统和方法中的毛刺减少
公开(公告)号：US5184032A
公开(公告)日：1993-02-02
申请号：US691266
申请日：1991-04-25
申请人： Jerald G. Leach
发明人： Jerald G. Leach
IPC分类号： H03K5/1252 , H03K17/16
CPC分类号： H03K17/165 , H03K5/1252
摘要： An integrated circuit has a clock input pad and circuitry operative in response to a clock signal. Clock transitions at the clock input pad are potentially subject to glitches due to noise and ringing. Further provided is a glitch remover circuit having a logic gate having first and second inputs. The glitch remover circuit has a series of circuits coupled to the clock input pad with differing delays for positive edges than for negative edges. The series of circuits has an output connected to the first input of the logic gate, with the second input coupled to the series of circuits intermediately. Other devices, systems and methods are also disclosed.
摘要翻译：集成电路具有响应于时钟信号而工作的时钟输入焊盘和电路。由于噪声和振铃，时钟输入板上的时钟转换可能会产生毛刺。另外提供一种毛刺去除器电路，其具有具有第一和第二输入的逻辑门。毛刺去除器电路具有连接到时钟输入板的一系列电路，其正边沿具有不同于负沿的延迟。该系列电路具有连接到逻辑门的第一输入端的输出，第二输入端连接到该系列电路。还公开了其他装置，系统和方法。

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