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1. 发明授权

US08507393B2 Low temperature co-fired ceramics with low dielectric loss for millimeter-wave application 有权
标题翻译：用于毫米波应用的低介电损耗的低温共烧陶瓷
公开(公告)号：US08507393B2
公开(公告)日：2013-08-13
申请号：US13098937
申请日：2011-05-02
申请人： Jeong Hyun Park , Jin Gu Kang , Young Jin Choi , Jae Gwan Park
发明人： Jeong Hyun Park , Jin Gu Kang , Young Jin Choi , Jae Gwan Park
IPC分类号： C03C14/00
CPC分类号： H01B3/12 , C03C8/02 , C03C14/004 , C03C2214/20 , C04B35/16 , C04B35/20 , C04B2235/3217 , C04B2235/3284 , C04B2235/3427 , C04B2235/3445 , C04B2235/365 , C04B2235/77 , C04B2235/96
摘要： Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4 (1) wherein 0≦x≦1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.
摘要翻译：提供一种电介质陶瓷组合物，其包含：40-70重量％的硼硅酸盐基玻璃料，其包含50-80摩尔％的SiO 2，15-20摩尔％的B 2 O 3，0.1-5摩尔％的一种或多种碱金属氧化物从Li 2 O和Na 2 O，以及0.1-30mol％的一种或多种选自MgO，CaO，SrO和ZnO的碱土金属氧化物; 和30-60重量％的由化学式1表示的陶瓷填料：（Zn1-xMgx）2SiO4（1），其中0≤x≤1。所公开的低温共烧陶瓷（LTCC）组合物在低温下是可烧结的，在800-900℃的温度范围内相对密度至少为95％，能够最小化电损耗，介电常数并且具有非常低的介电损耗，并且适用于60GHz以上的低频带至毫米波段。

2. 发明申请

US20080001273A1 Semiconductor package having optimal interval between bond fingers for reduced substrate size 审中-公开
标题翻译：半导体封装具有用于降低衬底尺寸的粘结指状件之间的最佳间隔
公开(公告)号：US20080001273A1
公开(公告)日：2008-01-03
申请号：US11647927
申请日：2006-12-29
申请人： Jeong Hyun Park
发明人： Jeong Hyun Park
IPC分类号： H01L23/02
CPC分类号： H01L23/49838 , H01L23/3121 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/0401 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/73204 , H01L2224/73265 , H01L2224/83 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor chip having a plurality of bonding pads, and a substrate having a first surface on which a plurality of bond fingers are arranged and a second surface on which ball lands connected to the bond fingers are formed. The bond fingers are arranged in a plurality of rows, and are formed in the shape of a polygon, such that overlapping surfaces of a bond finger of a row, which overlap with another bond finger of another row, have a constant slope, and overlapping surfaces of bond fingers arranged in the same row, which face each other, are sloped in opposite directions. Bond fingers of each row are positioned between the overlapping surfaces of bond fingers of another row, which face each other, such that the bond fingers of the rows are arranged in a zigzag pattern.
摘要翻译：半导体封装包括具有多个接合焊盘的半导体芯片，以及具有第一表面的基板，多个键合指状物被布置在该第一表面上，并且在该第二表面上形成有与接合指状物连接的平台。粘结指状物布置成多行，并且形成为多边形的形状，使得与另一行的另一粘结指状物重叠的一行的键合键的重叠表面具有恒定的斜率，并且重叠布置在同一排中的彼此面对的粘合指状物的表面在相反的方向上倾斜。每排的粘结指状物位于彼此面对的另一行的粘合指状物的重叠表面之间，使得行的粘结指状物以Z字形图案排列。

3. 发明授权

US08315064B2 Apparatus for detecting pattern alignment error 有权
标题翻译：用于检测图案对准误差的装置
公开(公告)号：US08315064B2
公开(公告)日：2012-11-20
申请号：US13098764
申请日：2011-05-02
申请人： Jeong Hyun Park
发明人： Jeong Hyun Park
IPC分类号： H05K7/00
CPC分类号： H05K3/4679 , H01L22/34 , H01L2924/0002 , H05K1/0268 , H05K3/4644 , H05K2201/0969 , H05K2201/09909 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
摘要： An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring.
摘要翻译：一种用于检测图案对准误差的装置包括：设置在第一绝缘构件上的第一导电图案，其中施加有第一导电图案的电源; 用于覆盖第一导电图案的第二绝缘构件; 布置在所述第二绝缘构件上的第二导电图案; 连接到第二导电图案并穿过第二绝缘构件的导电通孔; 以及设置在第一导电图案中的绝缘图案，用于响应于导电通孔的位置检测对准误差。用于检测图案对准误差的装置可以检测具有多层布线的装置中的下布线的对准。

4. 发明授权

US07965164B2 Multi-output transformer 有权
标题翻译：多输出变压器
公开(公告)号：US07965164B2
公开(公告)日：2011-06-21
申请号：US12137438
申请日：2008-06-11
申请人： Jeong Hyun Park , Jong Rak Kim
发明人： Jeong Hyun Park , Jong Rak Kim
IPC分类号： H01F27/28 , H01F27/30
CPC分类号： H01F27/325 , H01F30/04
摘要： In accordance with the present invention, a multi-output transformer includes a primary bobbin provided with one primary winding unit with one input terminal and one ground terminal; a secondary bobbin provided with n(n: positive integer) number of secondary winding units with two output terminals respectively; a primary coil wound around the one primary winding unit; secondary coils wound around each of the n secondary winding units; and a pair of cores inserted into insertion holes formed inside the primary bobbin and the secondary bobbin respectively to separate the primary bobbin and the secondary bobbin.
摘要翻译：根据本发明，多输出变压器包括：一个主线轴，其具有一个具有一个输入端子和一个接地端子的初级绕组单元; 具有分别具有两个输出端子的n（n：正整数）次级绕组单元的次级绕线筒; 缠绕在一个初级绕组单元上的初级线圈; 二次线圈缠绕在n个次级绕组单元的每一个上; 以及分别形成在主筒管和副筒管内的插入孔中的一对芯体，用于分离主筒管和副筒管。

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