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1. 发明授权

US07049713B2 Pulsed current generator circuit with charge booster 有权
标题翻译：脉冲电流发生器电路带充电助力器
公开(公告)号：US07049713B2
公开(公告)日：2006-05-23
申请号：US10734002
申请日：2003-12-10
申请人： Peter Cuevas , Gedaliahoo Krieger , Maurice Evans , Jens Ullmann
发明人： Peter Cuevas , Gedaliahoo Krieger , Maurice Evans , Jens Ullmann
IPC分类号： H02M3/06
CPC分类号： G01R31/2841
摘要： A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.
摘要翻译：用于向被测器件提供电流脉冲的脉冲电流发生器电路包括用于将电流施加到被测器件的电流源和用于从被测器件分流电流的受控电流分流器。提供升压电路，用于当受控电流分流器断开并且电流再次流过被测器件时，向被测器件提供升压电流，从而有助于与被测器件相关联的寄生电容的再充电。

2. 发明授权

US06842294B2 Catadioptric objective 失效
标题翻译：反射折射目标
公开(公告)号：US06842294B2
公开(公告)日：2005-01-11
申请号：US10118479
申请日：2002-04-08
申请人： Hubert Holderer , Ulrich Weber , Alexander Kohl , Toralf Gruner , Christoph Zaczek , Jens Ullmann , Martin Weiser , Bernhard Gellrich , Hartmut Muenker
发明人： Hubert Holderer , Ulrich Weber , Alexander Kohl , Toralf Gruner , Christoph Zaczek , Jens Ullmann , Martin Weiser , Bernhard Gellrich , Hartmut Muenker
IPC分类号： G02B17/08 , G03F7/20 , H01L21/027 , G02B3/00 , G02B17/00
CPC分类号： G02B17/0892 , G02B17/08 , G03F7/70225
摘要： A catadioptric objective comprises a plurality of lenses and at least two deflecting mirrors that have reflecting surfaces that are at a specific angle, in particular of 90°, to one another. The two deflecting mirrors are arranged with their reflecting surfaces on a common base member whose position in the objective can be set.
摘要翻译：反射折射物镜包括多个透镜和至少两个偏转镜，其具有彼此具有特定角度，特别是90°的反射表面。两个偏转镜被布置成其反射表面位于可以设置物镜中的位置的公共基座构件上。

3. 发明授权

US07602205B2 Electromigration tester for high capacity and high current 有权
标题翻译：电容测试仪用于高容量和高电流
公开(公告)号：US07602205B2
公开(公告)日：2009-10-13
申请号：US12033270
申请日：2008-02-19
申请人： Jens Ullmann
发明人： Jens Ullmann
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2858
摘要： An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.
摘要翻译：被测电子器件（DUT）可以并入具有与DUT并联连接的限压器的电路中。该电路包括具有与DUT串联连接的输出电流的受控电流源。电压限制器的特征在于，当输出电流使得DUT上的电压（Vdut）将超过特定的最大电压Vmax时，没有电压限制器就位，输出电流的至少一部分流过电压限制器，以便将Vdut限制为小于或等于Vmax。当输出电流使Vdut小于或等于Vmax时，电流不流过限压器。电路可以包括多个DUT，每个DUT与受控电流源的输出电流串联，其中限压器与每个DUT并联连接。

4. 发明授权

US07598760B1 High temperature ceramic die package and DUT board socket 有权
标题翻译：高温陶瓷模具封装和DUT板插座
公开(公告)号：US07598760B1
公开(公告)日：2009-10-06
申请号：US12124935
申请日：2008-05-21
申请人： Thomas G. Bensing , Adalberto M. Ramirez , Jens Ullmann , Jacob Herschmann , Robert J. Sylvia , Maurice C. Evans
发明人： Thomas G. Bensing , Adalberto M. Ramirez , Jens Ullmann , Jacob Herschmann , Robert J. Sylvia , Maurice C. Evans
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A strip-shaped package is provided that can accept a single die up to many dice. Conduction paths are printed (or otherwise integrally formed) thereon to the edge of the package, and a complementary socket may be provided that, in combination with the strip-shaped package, provides for electrical connection to test electronics without the use of package leads. The strip-shaped package may be made of ceramic or other temperature resistant material. The strip-shaped package may have at least one “well” location in which the die or dice may be affixed to the strip-shaped package. The strip may have notches configured to function as separators between the individual die housings (and related integrally-formed conduction paths).
摘要翻译：提供了一种条形包装，可以接受多达骰子的单个模具。导电路径在其上打印（或以其它方式一体形成）到封装的边缘，并且可以提供互补插座，其与条形封装组合提供电连接到测试电子器件而不使用封装引线。带状包装可以由陶瓷或其他耐温材料制成。条形包装可以具有至少一个“井”位置，其中模具或骰子可以固定到条形包装。带材可以具有构造成用作各个模具外壳（和相关的整体形成的导电路径）之间的隔板的凹口。

5. 发明授权

US07093937B2 Optical component and coating system for coating substrates for optical components 有权
标题翻译：用于光学部件涂覆基板的光学部件和涂层系统
公开(公告)号：US07093937B2
公开(公告)日：2006-08-22
申请号：US11052751
申请日：2005-02-09
申请人： Harry Bauer , Matthias Heller , Hans-Jochen Paul , Jens Ullmann , Patrick Scheible , Christoph Zaczek
发明人： Harry Bauer , Matthias Heller , Hans-Jochen Paul , Jens Ullmann , Patrick Scheible , Christoph Zaczek
IPC分类号： G02C7/02
CPC分类号： G02B1/10 , C23C14/0021 , C23C14/044 , C23C14/505
摘要： An optical component and a coating system for coating substrates for optical components with essentially rotationally symmetric coatings, the system having a planetary-drive system (1) that has a rotating planet carrier (2) and several planets (4), each of which carries a single substrate, that corotate both with the planet carrier and with respect to the primary carrier. In one embodiment a set of stationary first masks (20) that allow controlling the radial variation in physical film thickness is arranged between a source (8) of material situated beneath the planets and the substrates. A set of second masks that mask off evaporation angles exceeding a limiting evaporation or incidence angle (β max) for every substrate also corotate with the primary carrier (2), which allows depositing coatings having a prescribed radial film-thickness distribution and a virtually constant density of the coating material over their full radial extents for relatively low, and only slightly varying, evaporation angles.
摘要翻译：一种用于涂覆具有基本上旋转对称涂层的光学部件的基板的光学部件和涂层系统，该系统具有行星传动系统（1），其具有旋转的行星架（2）和几个行星（4），每个行星架单个衬底，其与行星架相关并且相对于主载体共转。在一个实施例中，允许控制物理膜厚度的径向变化的一组固定第一掩模（20）布置在位于行星下方的材料源（8）和基板之间。掩盖每个底物超过限制蒸发或入射角（βmax）的蒸发角度的一组第二掩模也与主载体（2）一致，这允许沉积具有规定径向膜厚度分布和实际上恒定的涂层在完全径向范围内涂层材料的密度相对较低且仅略微变化的蒸发角度。

6. 发明申请

US20090206869A1 ELECTROMIGRATION TESTER FOR HIGH CAPACITY AND HIGH CURRENT 有权
标题翻译：高容量和高电流电磁测试仪
公开(公告)号：US20090206869A1
公开(公告)日：2009-08-20
申请号：US12033270
申请日：2008-02-19
申请人： Jens Ullmann
发明人： Jens Ullmann
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.
摘要翻译：被测电子器件（DUT）可以并入具有与DUT并联连接的限压器的电路中。该电路包括具有与DUT串联连接的输出电流的受控电流源。电压限制器的特征在于，当输出电流使得DUT上的电压（Vdut）将超过特定的最大电压Vmax时，没有电压限制器就位，输出电流的至少一部分流过电压限制器，以便将Vdut限制为小于或等于Vmax。当输出电流使Vdut小于或等于Vmax时，电流不流过限压器。电路可以包括多个DUT，每个DUT与受控电流源的输出电流串联，其中限压器与每个DUT并联连接。

7. 发明申请

US20080315900A1 HIGH TEMPERATURE CERAMIC SOCKET CONFIGURED TO TEST PACKAGED SEMICONDUCTOR DEVICES 有权
标题翻译：配置到测试包装半导体器件的高温陶瓷插座
公开(公告)号：US20080315900A1
公开(公告)日：2008-12-25
申请号：US11766938
申请日：2007-06-22
申请人： Jose Ysaguirre , Jens Ullmann , Adalberto M. Ramirez , Robert J. Sylvia
发明人： Jose Ysaguirre , Jens Ullmann , Adalberto M. Ramirez , Robert J. Sylvia
IPC分类号： G01R1/073 , G01R31/02
CPC分类号： G01R1/0433
摘要： A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.
摘要翻译：测试插座组件用于测试集成电路。单件插座基本上由绝缘材料形成，并且具有形成在其中的多个孔，构造成容纳多个导电弹簧。单件插座的每个孔都具有单独的一个导电弹簧。测试插座包括被配置为接收集成电路的引线的多个引脚，测试插座的引脚延伸到单个插座的多个孔中，每个引脚与弹簧接合，其中单个插座位于所述多个孔与所述电路板上的电触点对齐，使得所述多个弹簧将所述触点和所述多个销电连接。单件插座基本上由诸如陶瓷的高温绝缘材料构成。

8. 发明授权

US07429856B1 Voltage source measurement unit with minimized common mode errors 有权
标题翻译：电压源测量单元，具有最小的共模误差
公开(公告)号：US07429856B1
公开(公告)日：2008-09-30
申请号：US11942964
申请日：2007-11-20
申请人： Jens Ullmann
发明人： Jens Ullmann
IPC分类号： G01R1/30
CPC分类号： G01R19/0092 , G01R15/146
摘要： A particular configuration of voltage source measurement (VSM) circuitry minimizes common mode errors in measurement of current through a device under test (DUT), even across a wide range of output voltages. The current IDUT is not affected by common-mode errors, since the current measurement is based on the output voltage of an operational amplifier or a differential amplifier, and the circuit configuration is such that the current measurement is made while the operation amplifier or differential amplifier has very low common-mode input voltage.
摘要翻译：电压源测量（VSM）电路的特定配置可最大限度地减少测试中被测器件（DUT）的电流中的共模误差，甚至在宽范围的输出电压范围内。由于电流测量基于运算放大器或差分放大器的输出电压，因此电流I DUT不受共模误差的影响，并且电路配置使得电流测量为而运算放大器或差分放大器具有非常低的共模输入电压。

9. 发明授权

US07602201B2 High temperature ceramic socket configured to test packaged semiconductor devices 有权
标题翻译：高温陶瓷插座配置用于测试封装的半导体器件
公开(公告)号：US07602201B2
公开(公告)日：2009-10-13
申请号：US11766938
申请日：2007-06-22
申请人： Jose Ysaguirre , Jens Ullmann , Adalberto M. Ramirez , Robert J. Sylvia
发明人： Jose Ysaguirre , Jens Ullmann , Adalberto M. Ramirez , Robert J. Sylvia
IPC分类号： G01R31/02 , H01R12/00 , H01K1/00
CPC分类号： G01R1/0433
摘要： A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.
摘要翻译：测试插座组件用于测试集成电路。单件插座基本上由绝缘材料形成，并且具有形成在其中的多个孔，构造成容纳多个导电弹簧。单件插座的每个孔都具有单独的一个导电弹簧。测试插座包括被配置为接收集成电路的引线的多个引脚，测试插座的引脚延伸到单个插座的多个孔中，每个引脚与弹簧接合，其中单个插座位于所述多个孔与所述电路板上的电触点对齐，使得所述多个弹簧将所述触点和所述多个销电连接。单件插座基本上由诸如陶瓷的高温绝缘材料构成。

10. 发明授权

US07172450B1 High temperature open ended zero insertion force (ZIF) test socket 有权
标题翻译：高温开放零插入力（ZIF）测试插座
公开(公告)号：US07172450B1
公开(公告)日：2007-02-06
申请号：US11306797
申请日：2006-01-11
申请人： Robert James Sylvia , Adalberto M. Ramirez , Jens Ullmann , Jose Ysaguirre , Peter P. Cuevas , Maurice C. Evans
发明人： Robert James Sylvia , Adalberto M. Ramirez , Jens Ullmann , Jose Ysaguirre , Peter P. Cuevas , Maurice C. Evans
IPC分类号： H01R4/50 , H01R13/625 , H01R12/00 , H05K1/00
CPC分类号： G01R1/0466 , H01R2201/20 , Y10S439/912
摘要： A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A support frame includes a first portion which physically engages the first member and a second portion which physically engages the second member. A lever or handle is attached to the second portion and includes a cam surface for engaging a cam follower on the first portion for imparting relative lateral motion between the two members whereby the package leads physically engage wires of the second member.
摘要翻译：一种用于测试具有引线的封装集成电路的插座，包括用于接收集成电路封装的第一部件，并且具有用于接收从封装延伸的引线的多个孔。第二构件具有用于接合引线的多个线触点，第一和第二构件布置成允许其相对的横向平移。支撑框架包括物理地接合第一构件的第一部分和物理地接合第二构件的第二部分。杆或手柄附接到第二部分并且包括凸轮表面，用于与第一部分上的凸轮从动件接合，以在两个构件之间施加相对的横向运动，由此包装引线物理地接合第二构件的线。

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