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1. 发明申请

US20090283810A1 Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production 有权
标题翻译：具有耐ESD电容器的集成电路布置及相应的生产方法
公开(公告)号：US20090283810A1
公开(公告)日：2009-11-19
申请号：US12511845
申请日：2009-07-29
申请人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
发明人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
IPC分类号： H01L29/94 , H03K3/01
CPC分类号： H01L29/94 , H01L27/0811
摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
摘要翻译：公开了一种在n型阱中包括电容器的电路装置。电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。任选地存在的辅助掺杂层确保电容器的高面积电容，尽管具有高的ESD强度。

2. 发明授权

US07986009B2 Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production 有权
公开(公告)号：US07986009B2
公开(公告)日：2011-07-26
申请号：US12511845
申请日：2009-07-29
申请人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
发明人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
IPC分类号： H01L23/62
摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

3. 发明申请

US20100163995A1 Semiconductor Device With Cooling Element 有权
标题翻译：带冷却元件的半导体器件
公开(公告)号：US20100163995A1
公开(公告)日：2010-07-01
申请号：US12720700
申请日：2010-03-10
申请人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
发明人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L23/367 , H01L27/0248 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed
摘要翻译：本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。还公开了其他实施例

4. 发明申请

US20070034959A1 Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production 审中-公开
标题翻译：具有耐ESD电容器的集成电路布置及相应的生产方法
公开(公告)号：US20070034959A1
公开(公告)日：2007-02-15
申请号：US11502262
申请日：2006-08-10
申请人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
发明人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
IPC分类号： H01L23/62
CPC分类号： H01L29/94 , H01L27/0811
摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
摘要翻译：公开了一种在n型阱中包括电容器的电路装置。电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。任选地存在的辅助掺杂层确保电容器的高面积电容，尽管具有高的ESD强度。

5. 发明授权

US09048096B2 Diode-based ESD concept for DEMOS protection 有权
标题翻译：基于二极管的ESD概念，用于DEMOS保护
公开(公告)号：US09048096B2
公开(公告)日：2015-06-02
申请号：US11844965
申请日：2007-08-24
申请人： Jens Schneider , Klaus Roeschlau , Harald Gossner
发明人： Jens Schneider , Klaus Roeschlau , Harald Gossner
IPC分类号： H01L23/62 , H01L27/02
CPC分类号： H01L27/0259 , H01L27/0255 , H01L29/0684 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/732 , H01L29/7833 , H02H9/041
摘要： The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.
摘要翻译：本发明涉及一种用于集成电路的ESD保护电路，其包括需要保护的漏极扩展MOS器件和输出焊盘。 ESD保护电路包括耦合到输出焊盘和偏置电压轨道的第一二极管，耦合到输出焊盘和另一个偏置电压轨道的第二二极管，以及耦合在两个偏置电压轨道之间的ESD功率钳位。 ESD功率钳位形成为垂直的npn晶体管，其基极和发射极耦合在一起。 npn晶体管的集电极使用n阱注入和DEMOS n漏极扩展形成，以产生基于快速恢复的电压限制特性。二极管由掩埋的n型层上的轻掺杂p型衬底区域和由插入衬底分离的p阱注入和n阱注入形成。第三二极管可以耦合在两个偏置电压轨道之间。

6. 发明授权

US08076728B2 Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production 有权
标题翻译：具有耐ESD电容器的集成电路布置及相应的生产方法
公开(公告)号：US08076728B2
公开(公告)日：2011-12-13
申请号：US12511845
申请日：2009-07-29
申请人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
发明人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
IPC分类号： H01L23/62
CPC分类号： H01L29/94 , H01L27/0811
摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
摘要翻译：公开了一种在n型阱中包括电容器的电路装置。电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。任选地存在的辅助掺杂层确保了电容器的高面积电容，尽管高度的ESD强度。

7. 发明申请

US20090140335A1 Drain-Extended Field Effect Transistor 有权
标题翻译：漏极扩展场效应晶体管
公开(公告)号：US20090140335A1
公开(公告)日：2009-06-04
申请号：US11950223
申请日：2007-12-04
申请人： Jens Schneider , Harald Gossner
发明人： Jens Schneider , Harald Gossner
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/1083 , H01L29/7831 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A drain-extended field effect transistor includes a drain contact region and a drain extension region. The drain-extended field effect transistor further includes an electrostatic discharge protection region that is electrically connected between the drain contact region and the drain extension region to protect the drain-extended field effect transistor against electrostatic discharge. The electrostatic discharge protection region has a dopant concentration level such that in case of an electrostatic discharge event, a base push-out is prevented from reaching the drain contact region.
摘要翻译：漏极扩展场效应晶体管包括漏极接触区域和漏极延伸区域。漏极扩展场效应晶体管还包括静电放电保护区域，其电连接在漏极接触区域和漏极延伸区域之间，以保护漏极扩展场效应晶体管免受静电放电。静电放电保护区域具有掺杂剂浓度水平，使得在静电放电事件的情况下，防止基极推出到达漏极接触区域。

8. 发明申请

US20090050970A1 Diode-Based ESD Concept for DEMOS Protection 有权
标题翻译：用于DEMOS保护的基于二极管的ESD概念
公开(公告)号：US20090050970A1
公开(公告)日：2009-02-26
申请号：US11844965
申请日：2007-08-24
申请人： Jens Schneider , Klaus Roeschlau , Harald Gossner
发明人： Jens Schneider , Klaus Roeschlau , Harald Gossner
IPC分类号： H01L23/62 , H01L21/8249
CPC分类号： H01L27/0259 , H01L27/0255 , H01L29/0684 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/732 , H01L29/7833 , H02H9/041
摘要： The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.
摘要翻译：本发明涉及一种用于集成电路的ESD保护电路，其包括需要保护的漏极扩展MOS器件和输出焊盘。 ESD保护电路包括耦合到输出焊盘和偏置电压轨道的第一二极管，耦合到输出焊盘和另一个偏置电压轨道的第二二极管，以及耦合在两个偏置电压轨道之间的ESD功率钳位。 ESD功率钳位形成为垂直的npn晶体管，其基极和发射极耦合在一起。 npn晶体管的集电极使用n阱注入和DEMOS n漏极扩展形成，以产生基于快速恢复的电压限制特性。二极管由掩埋的n型层上的轻掺杂p型衬底区域和由插入衬底分离的p阱注入和n阱注入形成。第三二极管可以耦合在两个偏置电压轨道之间。

9. 发明申请

US20080116515A1 MUGFET WITH INCREASED THERMAL MASS 有权
标题翻译： MUGFET具有增加的热质量
公开(公告)号：US20080116515A1
公开(公告)日：2008-05-22
申请号：US11561170
申请日：2006-11-17
申请人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
发明人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L23/367 , H01L27/0248 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed
摘要翻译：本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。还公开了其他实施例

10. 发明申请

US20050179088A1 ESD protective apparatus for a semiconductor circuit having an ESD protective circuit which makes contact with a substrate or guard ring contact 审中-公开
标题翻译：具有与衬底或保护环接触的ESD保护电路的半导体电路的ESD保护装置
公开(公告)号：US20050179088A1
公开(公告)日：2005-08-18
申请号：US11059778
申请日：2005-02-16
申请人： Ulrich Glaser , Harald Gossner , Jens Schneider , Martin Streibl , Silke Bargstadt-Franke
发明人： Ulrich Glaser , Harald Gossner , Jens Schneider , Martin Streibl , Silke Bargstadt-Franke
IPC分类号： H01L23/62 , H01L27/02
CPC分类号： H01L27/0266 , H01L27/0255
摘要： An electrostatic discharge (ESD) protective apparatus for a semiconductor circuit has at least one ESD protective element, which is connected between the substrate contact and a ground potential connection, and is electrically connected to the substrate contact. The ESD protective element may be in the form of an ESD protective diode or an ESD protective transistor. It is also possible to connect a resistor or an ESD protective transistor between the substrate contact and the ground potential connection as an ESD protective element, and additionally to connect an ESD protective diode or an ESD protective transistor between the substrate contact and a supply voltage potential connection.
摘要翻译：用于半导体电路的静电放电（ESD）保护装置具有至少一个ESD保护元件，其连接在基板触点和地电位连接之间，并且电连接到基板触点。 ESD保护元件可以是ESD保护二极管或ESD保护晶体管的形式。也可以在基板触点和接地电位连接之间连接一个电阻器或ESD保护晶体管作为ESD保护元件，另外还可以在基板触点和电源电压电位之间连接ESD保护二极管或ESD保护晶体管连接。

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