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1. 发明授权

US07340539B2 Device connected to a bus for storing information utilized to allocate priority to data stored in storage device and method for operating the device 有权
标题翻译：连接到总线的设备，用于存储用于分配存储在存储设备中的数据的优先级的信息和用于操作设备的方法
公开(公告)号：US07340539B2
公开(公告)日：2008-03-04
申请号：US10424177
申请日：2003-04-25
申请人： Jens Barrenscheen , Karl Herz , Achim Vowe
发明人： Jens Barrenscheen , Karl Herz , Achim Vowe
IPC分类号： G06F3/00 , G06F13/00 , G06F13/04
CPC分类号： H04L12/40032 , H04L12/40163 , H04L12/4135 , H04L49/90 , H04L2012/40215
摘要： A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.
摘要翻译：连接到总线的设备可以向一个或多个其他设备发送数据和/或可以通过总线从其他设备接收数据，包括要发送或接收的数据的存储器（即，存储器或存储器区域）临时存储的控制装置，以及确定是否要发送任何数据的控制装置，以及在适当的情况下存储下一个要发送的数据的存储和/或在哪个存储中存储接收的数据。通过总线发送的数据中不包含的信息存储在每个存储器中，并用于向相应的存储器分配优先级，并且控制装置考虑该信息以决定下一个要发送的数据的存储将被存储和/或存储接收到的数据的存储。

2. 发明授权

US06996646B2 Bus system 有权
公开(公告)号：US06996646B2
公开(公告)日：2006-02-07
申请号：US10116172
申请日：2002-04-04
申请人： Jens Barrenscheen , Karl Herz , Achim Vowe
发明人： Jens Barrenscheen , Karl Herz , Achim Vowe
IPC分类号： G06F13/36
CPC分类号： G06F13/364
摘要： A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

3. 发明授权

US07047155B2 Bus interface 有权
公开(公告)号：US07047155B2
公开(公告)日：2006-05-16
申请号：US10284807
申请日：2002-10-31
申请人： Jens Barrenscheen , Achim Vowe
发明人： Jens Barrenscheen , Achim Vowe
IPC分类号： G06F13/42
CPC分类号： G06F11/221 , H04J3/0694 , H04L12/40013
摘要： A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer provided in the bus interface or a timer provided in the chip that contains the bus interface is used to ascertain the timing of operations taking place within the bus interface and/or on the bus. This allows data required for configuring the bus interface to be acquired more simply, more quickly, more accurately and more comprehensively than is the case up to now. In addition, the bus interface is consequently able to match itself to the given circumstances.

4. 发明授权

US06292862B1 Bridge module 失效
标题翻译：桥模块
公开(公告)号：US06292862B1
公开(公告)日：2001-09-18
申请号：US09123825
申请日：1998-07-28
申请人： Jens Barrenscheen , Gunther Fenzl , Achim Vowe
发明人： Jens Barrenscheen , Gunther Fenzl , Achim Vowe
IPC分类号： G06F1300
CPC分类号： H04L49/9057 , H04L12/46 , H04L12/4625 , H04L49/90 , H04L2012/40215 , H04L2012/40273
摘要： The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single memory device is provided for buffer storage of the data during a data transfer. The data transfer, which is controlled exclusively by the data to be transmitted, is thus carried out in a simple manner and completely automatically, without the interposition of a processor unit. It is thereby possible very easily and thus also at an attractive cost to specify a module which is suitable for the data transfer between different bus systems.
摘要翻译：桥模块连接在至少两个总线系统之间，适用于从一个总线系统到另一个总线系统的二进制数据的串行数据传输。提供单个存储器件用于在数据传输期间缓冲存储数据。因此，仅由所传送的数据进行控制的数据传送就能以简单的方式完全自动进行，而不需要插入处理器单元。因此，可以非常容易地并且因此也以有吸引力的成本来指定适合于不同总线系统之间的数据传输的模块。

5. 发明授权

US09098393B2 Interface for ensuring efficient data requests 有权
标题翻译：用于确保有效数据请求的接口
公开(公告)号：US09098393B2
公开(公告)日：2015-08-04
申请号：US10116490
申请日：2002-04-04
申请人： Jens Barrenscheen , Karl Herz
发明人： Jens Barrenscheen , Karl Herz
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F12/08 , G06F3/06 , G06F13/16
CPC分类号： G06F12/0215 , G06F3/0601 , G06F3/0602 , G06F3/0628 , G06F3/0635 , G06F12/00 , G06F12/02 , G06F12/063 , G06F12/0862 , G06F13/161 , G06F2212/2022
摘要： The interface between a memory device and a device requesting data from the memory device ensures that the data requested are read from the memory device and forwarded to the device requesting the data. The interface described is distinguished by the fact that if, following the reading of data from the memory device, there are no further requests from the device requesting data, it modifies the address previously used to read data from the memory device and arranges for the data stored at the address in the memory device to be read, and/or in that, at a predefined time following the initiation of the read operation, it accepts the data output by the memory device and/or starts the next memory access.
摘要翻译：存储器件与从存储器件请求数据的器件之间的接口确保从存储器件读取所请求的数据并转发给请求数据的器件。所描述的接口的区别在于，如果在从存储器件读取数据之后，没有来自设备请求数据的进一步的请求，则其修改先前用于从存储器件读取数据的地址并排列数据存储在要读取的存储器件中的地址处，和/或在读操作开始之后的预定时间，它接受由存储器件输出的数据和/或开始下一个存储器访问。

6. 发明授权

US08533543B2 System for testing connections between chips 有权
标题翻译：用于测试芯片之间连接的系统
公开(公告)号：US08533543B2
公开(公告)日：2013-09-10
申请号：US12414394
申请日：2009-03-30
申请人： Jens Barrenscheen , Harry Siebert
发明人： Jens Barrenscheen , Harry Siebert
IPC分类号： G01R31/28
CPC分类号： G01R31/046 , G01R31/31717
摘要： In accordance with an aspect of the application, there is provided a system for testing, including a first chip, a second chip, and first and second connections. The first connection is configured to couple a first pin of the first chip to a first pin of the second chip, and to transmit an initial signal from the first chip to the second chip. The second connection is configured to couple a second pin of the first chip to a second pin of the second chip to return the signal as a returned signal to the first chip. The first chip comprises comparison circuitry configured to compare the returned signal with the initial signal.
摘要翻译：根据应用的一个方面，提供了一种用于测试的系统，包括第一芯片，第二芯片以及第一和第二连接。第一连接被配置为将第一芯片的第一引脚耦合到第二芯片的第一引脚，并将初始信号从第一芯片传输到第二芯片。第二连接被配置为将第一芯片的第二引脚耦合到第二芯片的第二引脚，以将信号作为返回信号返回到第一芯片。第一芯片包括比较电路，其被配置为将返回的信号与初始信号进行比较。

7. 发明申请

US20130187656A1 Methods for Monitoring Functionality of a Switch and Driver Units for Switches 有权
标题翻译：用于监控交换机功能和开关驱动单元的方法
公开(公告)号：US20130187656A1
公开(公告)日：2013-07-25
申请号：US13356343
申请日：2012-01-23
申请人： Jens Barrenscheen , Laurent Beaurenaut
发明人： Jens Barrenscheen , Laurent Beaurenaut
IPC分类号： G01R31/327
CPC分类号： H03K17/28 , G01R31/3275
摘要： A gate driver unit includes an input stage, an output stage, a read/write interface, and a monitoring stage. The input stage is configured to receive control signals and forward the control signals to the output stage and the monitoring stage. The read/write interface is configured to receive configuration data and forward the configuration data to the monitoring stage. The monitoring stage is configured to capture and evaluate signals of a power switch connected to the gate driver unit and synchronize the evaluation of the signals of the power switch to the control signals. The evaluation of the signals and the synchronization of the evaluation are based on the configuration data.
摘要翻译：门驱动器单元包括输入级，输出级，读/写接口和监控级。输入级被配置为接收控制信号并将控制信号转发到输出级和监控级。读/写接口配置为接收配置数据并将配置数据转发到监控级。监控级被配置为捕获和评估连接到栅极驱动器单元的电源开关的信号，并且将功率开关的信号的评估同步到控制信号。信号的评估和评估的同步基于配置数据。

8. 发明授权

US07907431B2 Devices and methods for converting or buffering a voltage 有权
标题翻译：用于转换或缓冲电压的装置和方法
公开(公告)号：US07907431B2
公开(公告)日：2011-03-15
申请号：US12182012
申请日：2008-07-29
申请人： Jens Barrenscheen , Marcus Nuebling , Werner Roessler
发明人： Jens Barrenscheen , Marcus Nuebling , Werner Roessler
IPC分类号： H02M3/335 , H02M7/44
CPC分类号： B60W10/08 , H01F37/00 , H01H47/00 , H02M3/1582 , H02M2003/1555
摘要： Embodiments of the invention relate to devices and methods for converting or buffering a voltage including an inductor configured to perform at least a primary function and to be reused to contribute to converting or buffering the voltage as a secondary function.
摘要翻译：本发明的实施例涉及用于转换或缓冲包括电感器的电压的装置和方法，所述电感器被配置为执行至少主要功能并被重新用于有助于转换或缓冲作为次要功能的电压。

9. 发明授权

US07733259B2 System having a signal converter device and method of operating 有权
标题翻译：具有信号转换器装置和操作方法的系统
公开(公告)号：US07733259B2
公开(公告)日：2010-06-08
申请号：US12349790
申请日：2009-01-07
申请人： Jens Barrenscheen , Patrick Leteinturier
发明人： Jens Barrenscheen , Patrick Leteinturier
IPC分类号： H03M1/66
CPC分类号： G06F3/05
摘要： A system having a signal converter device, and a method for operating a system having a signal converter device is disclosed. One embodiment provides loading a capacitive device to a preparation voltage in a first operating phase, and loading the capacitive device to a measuring voltage in a second operating phase after the first operating phase.
摘要翻译：公开了一种具有信号转换器装置的系统和一种用于操作具有信号转换器装置的系统的方法。一个实施例提供了在第一操作阶段将电容性装置加载到制备电压，并且在第一操作阶段之后的第二操作阶段将电容性装置加载到测量电压。

10. 发明授权

US07702822B2 Process for operating a system module and semi-conductor component 有权
标题翻译：操作系统模块和半导体组件的过程
公开(公告)号：US07702822B2
公开(公告)日：2010-04-20
申请号：US11288441
申请日：2005-11-29
申请人： Jens Barrenscheen
发明人： Jens Barrenscheen
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04L12/403 , H04L2012/40234
摘要： The invention relates to a semi-conductor component, in particular a semi-conductor component configured to be connected with a bus, in particular a LIN bus system, as well as a process for operating a system module, configured to be connected with a bus, in particular a LIN bus system, which includes emitting a data record and allocated check bits while operating the system module in a first operating mode, such that to operate the system module in a second operating mode, check bits differently generated in comparison with the first operating mode are used.
摘要翻译：本发明涉及半导体部件，特别是被配置为与总线连接的半导体部件，特别是LIN总线系统，以及用于操作系统模块的过程，该系统模块被配置为与总线特别是LIN总线系统，其包括在以第一操作模式操作系统模块时发射数据记录和分配的校验位，使得以第二操作模式操作系统模块，检查与使用第一操作模式。

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