专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 再颁专利

USRE44010E1 Modular base station with variable communication capacity 失效
标题翻译：具有可变通信能力的模块化基站
公开(公告)号：USRE44010E1
公开(公告)日：2013-02-19
申请号：US12023611
申请日：1999-03-17
申请人： Jeffrey S. Polan , Stephen G. Dick , Leonid Kazakevich , Fatih M. Ozluturk , Robert T. Regis , Richard Turner
发明人： Jeffrey S. Polan , Stephen G. Dick , Leonid Kazakevich , Fatih M. Ozluturk , Robert T. Regis , Richard Turner
IPC分类号： H04B7/216
CPC分类号： H04W72/005 , H04B17/318 , H04B17/382 , H04W16/12 , H04W52/322 , H04W52/325
摘要： The present invention provides a base station architecture that is modular in configuration, lowering the initial cost of implementing a new CDMA telecommunication system for a defined geographical region while allowing for future capacity. The scalable architecture is assembled from a digital base station unit that is configured to support a plurality of simultaneous wireless calls connecting to a conventional public switched telephone network. For initial startup, two base station units are deployed for redundancy in case of a single failure. Additional base station units may be added when the need arises for extra traffic capacity. If sectorization is required, the base station units may be directionally oriented. Coupled to and remote from each base station unit are two amplified antenna modules that contain an omni-directional or an external directional antenna, a high power RF amplifier for transmitted frequencies and a low noise amplifier for received frequencies. A separate power supply module capable of supporting two base station units provides continued service in the event of a mains power outage.
摘要翻译：本发明提供了一种模块化配置的基站架构，降低了为所定义的地理区域实施新的CDMA电信系统的初始成本，同时允许将来的容量。可扩展架构由数字基站单元组合，数字基站单元被配置为支持连接到常规公共交换电话网络的多个同时无线呼叫。对于初始启动，在单个故障的情况下，部署了两个基站单元以实现冗余。当需要额外的流量时，可以添加额外的基站单元。如果需要扇区化，则基站单元可以是定向的。耦合到每个基站单元并且远离每个基站单元的两个放大天线模块包含全向或外部定向天线，用于发射频率的高功率RF放大器和用于接收频率的低噪声放大器。能够支持两个基站单元的单独的电源模块在主电源中断的情况下提供持续的服务。

2. 发明授权

US06993001B1 Modular base station with variable communication capacity 失效
公开(公告)号：US06993001B1
公开(公告)日：2006-01-31
申请号：US09646371
申请日：1999-03-17
申请人： Jeffrey Polan , Stephen G. Dick , Leonid Kazakevich , Fatih M. Ozluturk , Robert T. Regis , Richard Turner
发明人： Jeffrey Polan , Stephen G. Dick , Leonid Kazakevich , Fatih M. Ozluturk , Robert T. Regis , Richard Turner
IPC分类号： H04Q7/216
CPC分类号： H04W72/005 , H04B17/318 , H04B17/382 , H04W16/12 , H04W52/322 , H04W52/325
摘要： The present invention provides a base station architecture that is modular in configuration, lowering the initial cost of implementing a new CDMA telecommunication system for a defined geographical region while allowing for future capacity. The scalable architecture is assembled from a digital base station unit that is configured to support a plurality of simultaneous wireless calls connecting to a conventional public switched telephone network. For initial startup, two base station units are deployed for redundancy in case of a single failure. Additional base station units may be added when the need arises for extra traffic capacity. If sectorization is required, the base station units may be directionally oriented. Coupled to and remote from each base station unit are two amplified antenna modules that contain an omni-directional or an external directional antenna, a high power RF amplifier for transmitted frequencies and a low noise amplifier for received frequencies. A separate power supply module capable of supporting two base station units provides continued service in the event of a mains power outage.

3. 发明授权

US06405272B1 System and method for arbitration of a plurality of processing modules 失效
标题翻译：用于多个处理模块的仲裁的系统和方法
公开(公告)号：US06405272B1
公开(公告)日：2002-06-11
申请号：US09079600
申请日：1998-05-15
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： G06F13368
CPC分类号： H04B1/7075 , G06F13/374 , G06F13/376 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B2201/70702
摘要： An arbitration system which allows communication between a plurality of competing processing modules over a shared communication bus. The system comprises an arbitration line coupled to a controller located on each processing module. When a processing module desires access to the communication bus, each controller, executing the same arbitration protocol, shifts its respective module address onto the arbitration line and monitors the arbitration line to detect for collisions.
摘要翻译：一种允许通过共享通信总线在多个竞争处理模块之间进行通信的仲裁系统。该系统包括耦合到位于每个处理模块上的控制器的仲裁线。当处理模块期望访问通信总线时，执行相同仲裁协议的每个控制器将其各自的模块地址移动到仲裁线路上，并监视仲裁线路以检测冲突。

4. 发明授权

US06907024B2 Efficient multichannel filtering for CDMA modems 失效
公开(公告)号：US06907024B2
公开(公告)日：2005-06-14
申请号：US10304308
申请日：2002-11-25
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： G06F17/10 , H03H17/02 , H03H17/06 , H04B1/707 , H04B1/7075 , H04B1/708 , H04B1/7093 , H04B7/216
CPC分类号： H04B1/7075 , H03H17/0226 , H03H17/06 , H04B1/707 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B1/7093 , H04B2201/70702 , H04B2201/70707
摘要： An efficient, multichannel filter for CDMA modems permits multiple serial, digital bit streams to be filtered by digital signal processing techniques including sample weighting and summing functions. Each individual channel may have custom weighting coefficients or weighting coefficients common for all channels. If the weighting coefficients are by adaption, the same approach may be taken. The multichannel FIR filter is implemented with no multipliers and a reduction in the number of adders. To increase the speed of operation, the filter structure utilizes look-up tables storing the weighting coefficients. The invention can be embodied as either as a field programmable gate array or an application specific integrated circuit. The use of look-up tables saves significant chip resources.

5. 发明授权

US07631027B2 Efficient multichannel filtering for CDMA modems 失效
标题翻译： CDMA调制解调器的高效多信道滤波
公开(公告)号：US07631027B2
公开(公告)日：2009-12-08
申请号：US11141622
申请日：2005-05-31
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： G06F17/10 , H04B7/216
CPC分类号： H04B1/7075 , H03H17/0226 , H03H17/06 , H04B1/707 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B1/7093 , H04B2201/70702 , H04B2201/70707
摘要： An efficient, multichannel filter for CDMA modems permits multiple serial, digital bit streams to be filtered by digital signal processing techniques including sample weighting and summing functions. Each individual channel may have custom weighting coefficients or weighting coefficients common for all channels. If the weighting coefficients are by adaption, the same approach may be taken. The multichannel FIR filter is implemented with no multipliers and a reduction in the number of adders. To increase the speed of operation, the filter structure utilizes look-up tables storing the weighting coefficients. The invention can be embodied as either as a field programmable gate array or an application specific integrated circuit. The use of look-up tables saves significant chip resources.
摘要翻译：用于CDMA调制解调器的有效的多通道滤波器允许通过包括采样加权和求和功能的数字信号处理技术对多个串行数字比特流进行滤波。每个单独的通道可以具有对于所有通道共同的自定义加权系数或加权系数。如果通过适应加权系数，则可以采用相同的方法。多通道FIR滤波器没有乘法器并且减少加法器的数量。为了提高操作速度，滤波器结构利用存储加权系数的查找表。本发明可以被实现为现场可编程门阵列或专用集成电路。查找表的使用节省了大量的芯片资源。

6. 发明授权

US06823412B2 System and method for arbitration of a plurality of processing modules 有权
标题翻译：用于多个处理模块的仲裁的系统和方法
公开(公告)号：US06823412B2
公开(公告)日：2004-11-23
申请号：US10166216
申请日：2002-06-10
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： G06F13368
CPC分类号： H04B1/7075 , G06F13/374 , G06F13/376 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B2201/70702
摘要： Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.
摘要翻译：用于在复杂数字处理环境中的微处理器模块之间提供高速通信的仲裁高速控制数据总线系统的方法和装置。该系统具有简化的硬件架构，具有快速FIFO排队，TTL CMOS兼容级时钟信号，单总线主机仲裁，同步时钟，DMA和多处理器系统的独特模块寻址。该系统包括一个并行数据总线，共享总线主机驻留在每个处理模块上，处理通信和数据传输协议。 Bur仲裁通过专用的独立串行仲裁线执行。每个请求模块通过将请求模块的地址置于仲裁线路上并监视仲裁线路进行冲突来竞争对并行数据总线的访问，从而消除对总线请求和总线授权信号的需要。

7. 发明授权

US06487190B1 Efficient multichannel filtering for CDMA modems 失效
标题翻译： CDMA调制解调器的高效多信道滤波
公开(公告)号：US06487190B1
公开(公告)日：2002-11-26
申请号：US08670160
申请日：1996-06-27
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： H04B7216
CPC分类号： H04B1/7075 , H03H17/0226 , H03H17/06 , H04B1/707 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B1/7093 , H04B2201/70702 , H04B2201/70707
摘要： An efficient, multichannel filter for CDMA modems permits multiple serial, digital bit streams to be filtered by digital signal processing techniques including sample weighting and summing functions. Each individual channel may have custom weighting coefficients or weighting coefficients common for all channels. If the weighting coefficients are by adapation, the same approach may be taken. The multichannel FIR filter is implemented with no multipliers and a reduction in the number of adders. To increase the speed of operation, the filter structure utilizes look-up tables storing the weighting coefficients. The invention can be embodied as either as a field programmable gate array or an application specific integrated circuit. The use of look-up tables saves significant chip resources.
摘要翻译：用于CDMA调制解调器的有效的多通道滤波器允许通过包括采样加权和求和功能的数字信号处理技术对多个串行数字比特流进行滤波。每个单独的通道可以具有对于所有通道共同的自定义加权系数或加权系数。如果通过适应加权系数，则可以采用相同的方法。多通道FIR滤波器没有乘法器并且减少加法器的数量。为了提高操作速度，滤波器结构利用存储加权系数的查找表。本发明可以被实现为现场可编程门阵列或专用集成电路。查找表的使用节省了大量的芯片资源。

8. 发明授权

US5754803A Parallel packetized intermodule arbitrated high speed control and data bus 失效
标题翻译：并行打包模块仲裁高速控制和数据总线
公开(公告)号：US5754803A
公开(公告)日：1998-05-19
申请号：US671221
申请日：1996-06-27
申请人： Robert T. Regis
发明人： Robert T. Regis
IPC分类号： G06F13/376 , G06F13/374 , H04B1/7075 , H04B1/708 , G06F13/36
CPC分类号： H04B1/7075 , G06F13/374 , G06F13/376 , H04B1/70753 , H04B1/70755 , H04B1/70758 , H04B1/708 , H04B2201/70702
摘要： A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.
摘要翻译：并行分组式串联仲裁高速控制数据总线系统，允许在更复杂的数字处理环境中的微处理器模块之间进行高速通信。该系统具有简化的硬件体系结构，具有12.5 MHz快速FIFO排队，TTL CMOS兼容级别时钟信号，单总线主仲裁，同步时钟，DMA和多处理器系统的独特模块寻址。该系统包括并行数据总线，共享总线主机驻留在每个处理模块上，判定通信和数据传输协议。总线仲裁通过专用串行仲裁线执行，并且每个请求模块通过将请求模块的地址放置在仲裁线上并监视仲裁线路进行冲突来竞争对并行数据总线的访问。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式