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1. 发明授权

US08456249B2 Micro-scale system to provide thermal isolation and electrical communication between substrates 有权
标题翻译：微尺度系统提供基板之间的热隔离和电气通信
公开(公告)号：US08456249B2
公开(公告)日：2013-06-04
申请号：US13105735
申请日：2011-05-11
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Yu-Hua Lin , Robert L. Borwick , Alexandros P. Papavasiliou
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Yu-Hua Lin , Robert L. Borwick , Alexandros P. Papavasiliou
IPC分类号： H01S1/06 , H03B17/00
CPC分类号： H01S1/06 , B05D3/10 , B05D5/00 , B32B3/10 , B32B3/12 , B32B3/30 , B32B15/08 , B81B3/0081 , B81B7/0006 , C23F1/00 , G04F5/14 , H01S1/02 , H05K1/14 , Y10T428/24149 , Y10T428/24331 , Y10T428/24521 , Y10T428/24545
摘要： A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap.
摘要翻译：微型设备包括具有从带的第一侧延伸的增强结构的微尺寸刚性聚对二甲苯带，通过微尺寸刚性聚对二甲苯带悬挂的第一硅衬底，与第一衬底共形耦合的微尺寸刚性聚对二甲苯带和第二衬底保形地耦合到微尺寸刚性聚对二甲苯带，以悬浮第一硅衬底通过微尺寸刚性聚对二甲苯带。

2. 发明授权

US08187972B2 Through-substrate vias with polymer fill and method of fabricating same 有权
标题翻译：具有聚合物填充物的通孔衬底及其制造方法
公开(公告)号：US08187972B2
公开(公告)日：2012-05-29
申请号：US13014585
申请日：2011-01-26
申请人： Philip A. Stupar , Jeffrey F. DeNatale , Robert L. Borwick, III , Alexandros P. Papavasiliou
发明人： Philip A. Stupar , Jeffrey F. DeNatale , Robert L. Borwick, III , Alexandros P. Papavasiliou
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2224/131 , H01L2224/16145 , H01L2924/12044 , H01L2924/00014 , H01L2924/014
摘要： An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.
摘要翻译：通过衬底通孔的制造方法需要在半导体衬底中形成贯穿衬底通孔，使用ALD将电绝缘的，连续的和基本上共形的隔离材料沉积到衬底和通孔的内壁上，将导电材料沉积到通孔以及使用ALD的隔离材料，使得其在通孔的长度上是电连续的，并且在导电材料上沉积聚合物材料，使得存在于通孔中的任何连续的顶部至底部开口由聚合物填充材料。可以扩展基本制造方法以提供具有多个导电层的通孔，例如同轴和三轴通孔。

3. 发明申请

US20100110607A1 Vertical capacitors and method of fabricating same 有权
标题翻译：垂直电容器及其制造方法
公开(公告)号：US20100110607A1
公开(公告)日：2010-05-06
申请号：US12291263
申请日：2008-11-05
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
IPC分类号： H01G4/06 , H01L21/20 , H01L21/4763 , H01L21/02 , H01L21/31 , H01L21/44
CPC分类号： H01L28/90 , H01G4/012 , H01G4/236 , H01G4/33 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.
摘要翻译：一种在衬底中形成垂直电容器的制造方法。该方法优选是全干法，其包括在衬底中形成贯穿衬底通孔，使用原子层沉积（ALD）将第一导电材料层沉积到通孔中，使得其在通过使用ALD在所述第一导电层上沉积电绝缘的，连续的和基本上共形的隔离材料层，以及使用ALD在所述隔离材料层上沉积第二导电材料层，使得其在所述通孔的长度上是电连续的。这些层被布置成使得它们形成垂直电容器。本方法可以在小于200℃的温度下成功地实施，从而避免损坏可能出现的衬底上的电路。

4. 发明申请

US20100001378A1 Through-substrate vias and method of fabricating same 审中-公开
标题翻译：贯通衬底通孔及其制造方法
公开(公告)号：US20100001378A1
公开(公告)日：2010-01-07
申请号：US12217217
申请日：2008-07-01
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, and depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole. The isolation material may be prepared by activating it with a seed layer deposited by ALD. The via hole is preferably formed by dry etching first and second cavities having respective diameters into the substrate's top and bottom surfaces, respectively, to form a single continuous aperture through the substrate. The present method may be practiced at temperatures of less than 200° C. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.
摘要翻译：通过基板通孔的制造方法需要在半导体基板中形成贯通基板通孔，使用ALD将电绝缘的，连续的和基本上共形的隔离材料沉积在基板和通孔的内壁上，并将导电材料沉积到通过和使用ALD的隔离材料，使得其在通孔的长度上是电连续的。隔离材料可以通过用由ALD沉积的种子层激活来制备。通孔优选通过将具有各自直径的第一和第二空腔分别干蚀刻到基板的顶部和底部表面中，以形成通过基板的单个连续孔而形成。本方法可以在小于200℃的温度下实施。可以扩展基本制造方法以提供具有多个导电层的通孔，例如同轴和三轴通孔。

5. 发明授权

US08088667B2 Method of fabricating vertical capacitors in through-substrate vias 有权
标题翻译：在通孔中制造垂直电容器的方法
公开(公告)号：US08088667B2
公开(公告)日：2012-01-03
申请号：US12291263
申请日：2008-11-05
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Alexandros P. Papavasiliou , Robert L. Borwick, III
IPC分类号： H01L21/443
CPC分类号： H01L28/90 , H01G4/012 , H01G4/236 , H01G4/33 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.
摘要翻译：一种在衬底中形成垂直电容器的制造方法。该方法优选是全干法，其包括在衬底中形成贯穿衬底通孔，使用原子层沉积（ALD）将第一导电材料层沉积到通孔中，使得其在通过使用ALD在所述第一导电层上沉积电绝缘的，连续的和基本上共形的隔离材料层，以及使用ALD在所述隔离材料层上沉积第二导电材料层，使得其在所述通孔的长度上是电连续的。这些层被布置成使得它们形成垂直电容器。本方法可以在小于200℃的温度下成功地实施，从而避免损坏可能出现的衬底上的电路。

6. 发明申请

US20110121427A1 THROUGH-SUBSTRATE VIAS WITH POLYMER FILL AND METHOD OF FABRICATING SAME 有权
标题翻译：具有聚合物薄膜的基底层VIAS及其制造方法
公开(公告)号：US20110121427A1
公开(公告)日：2011-05-26
申请号：US13014585
申请日：2011-01-26
申请人： Philip A. Stupar , Jeffrey F. DeNatale , Robert L. Borwick, III , Alexandros P. Papavasiliou
发明人： Philip A. Stupar , Jeffrey F. DeNatale , Robert L. Borwick, III , Alexandros P. Papavasiliou
IPC分类号： H01L23/48 , H01L21/441 , H01L21/768 , H01L21/02 , H01L29/92
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2224/131 , H01L2224/16145 , H01L2924/12044 , H01L2924/00014 , H01L2924/014
摘要： An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.
摘要翻译：通过衬底通孔的制造方法需要在半导体衬底中形成贯穿衬底通孔，使用ALD将电绝缘的，连续的和基本上共形的隔离材料沉积到衬底和通孔的内壁上，将导电材料沉积到通孔以及使用ALD的隔离材料，使得其在通孔的长度上是电连续的，并且在导电材料上沉积聚合物材料，使得存在于通孔中的任何连续的顶部至底部开口由聚合物填充材料。可以扩展基本制造方法以提供具有多个导电层的通孔，例如同轴和三轴通孔。

7. 发明申请

US20120286884A1 Micro-scale System to Provide Thermal Isolation and Electrical Communication Between Substrates 有权
标题翻译：微尺度系统提供基板之间的热隔离和电气通信
公开(公告)号：US20120286884A1
公开(公告)日：2012-11-15
申请号：US13105735
申请日：2011-05-11
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Yu-Hua Lin , Robert L. Borwick , Alexandros P. Papavasiliou
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Yu-Hua Lin , Robert L. Borwick , Alexandros P. Papavasiliou
IPC分类号： H01S1/02 , B05D5/00 , B05D3/10 , H05K1/14 , B32B3/12 , B32B15/08 , B32B3/10 , C23F1/00 , B32B3/30
CPC分类号： H01S1/06 , B05D3/10 , B05D5/00 , B32B3/10 , B32B3/12 , B32B3/30 , B32B15/08 , B81B3/0081 , B81B7/0006 , C23F1/00 , G04F5/14 , H01S1/02 , H05K1/14 , Y10T428/24149 , Y10T428/24331 , Y10T428/24521 , Y10T428/24545
摘要： A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap.
摘要翻译：微型设备包括具有从带的第一侧延伸的增强结构的微尺寸刚性聚对二甲苯带，通过微尺寸刚性聚对二甲苯带悬挂的第一硅衬底，与第一衬底共形耦合的微尺寸刚性聚对二甲苯带和第二衬底保形地耦合到微尺寸刚性聚对二甲苯带，以悬浮第一硅衬底通过微尺寸刚性聚对二甲苯带。

8. 发明授权

US08742308B2 Imaging array device structure with separate charge storage capacitor layer 有权
标题翻译：成像阵列器件结构具有独立的电荷存储电容层
公开(公告)号：US08742308B2
公开(公告)日：2014-06-03
申请号：US12968811
申请日：2010-12-15
申请人： Jeffrey F. DeNatale , David J. Gulbransen , William E. Tennant , Alexandros P. Papavasiliou
发明人： Jeffrey F. DeNatale , David J. Gulbransen , William E. Tennant , Alexandros P. Papavasiliou
IPC分类号： H01L27/00 , G05D23/20 , G01J1/46
CPC分类号： G05D23/2036 , G01J1/46 , H01L27/14665
摘要： An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.
摘要翻译：成像阵列包括光电检测器层，读出IC（ROIC）层和与光电检测器和ROIC层不同的电荷存储电容器层; 这些层电互连以形成阵列。电荷存储电容层内的电容器优选是微加工的; 电荷存储电容器层可以是插入层或外层。

9. 发明申请

US20120153122A1 Imaging Array With Separate Charge Storage Capacitor Layer 有权
标题翻译：具有独立电荷存储电容层的成像阵列
公开(公告)号：US20120153122A1
公开(公告)日：2012-06-21
申请号：US12968811
申请日：2010-12-15
申请人： Jeffrey F. DeNatale , David J. Gulbransen , William E. Tennant , Alexandros P. Papavasiliou
发明人： Jeffrey F. DeNatale , David J. Gulbransen , William E. Tennant , Alexandros P. Papavasiliou
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： G05D23/2036 , G01J1/46 , H01L27/14665
摘要： An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.
摘要翻译：成像阵列包括光电检测器层，读出IC（ROIC）层和与光电检测器和ROIC层不同的电荷存储电容器层; 这些层电互连以形成阵列。电荷存储电容层内的电容器优选是微加工的; 电荷存储电容器层可以是插入层或外层。

10. 发明申请

US20080037103A1 Nanolaminate deformable mirrors 失效
标题翻译： Naminaminate可变形镜
公开(公告)号：US20080037103A1
公开(公告)日：2008-02-14
申请号：US11501590
申请日：2006-08-08
申请人： Alexandros P. Papavasiliou , Scot S. Olivier
发明人： Alexandros P. Papavasiliou , Scot S. Olivier
IPC分类号： G02B26/00
CPC分类号： G02B26/0841
摘要： A deformable mirror formed out of two layers of a nanolaminate foil attached to a stiff substrate is introduced. Deformation is provided by an electrostatic force between two of the layers. The internal stiffness of the structure allows for high-spatial-frequency shapes. The nanolaminate foil of the present invention allows for a high-quality mirror surface. The device achieves high precision in the vertical direction by using foils with accurately controlled thicknesses, but does not require high precision in the lateral dimensions, allowing such mirrors to be fabricated using crude lithography techniques. Such techniques allow structures up to about the meter scale to be fabricated.
摘要翻译：引入由两层附着在刚性基材上的纳米层压箔形成的可变形反射镜。变形由两层之间的静电力提供。结构的内部刚度允许高空间频率形状。本发明的纳米脂肪酸箔允许高质量的镜面。该装置通过使用具有精确控制厚度的箔而在垂直方向上实现高精度，但是不需要在侧向尺寸上的高精度，允许使用粗光刻技术来制造这样的反射镜。这种技术允许制造高达约计量表的结构。

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