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1. 发明授权

US6045678A Formation of nanofilament field emission devices 失效
标题翻译：纳米丝场发射装置的形成
公开(公告)号：US6045678A
公开(公告)日：2000-04-04
申请号：US847088
申请日：1997-05-01
申请人： Jeffrey D. Morse , Robert J. Contolini , Ronald G. Musket , Anthony F. Bernhardt
发明人： Jeffrey D. Morse , Robert J. Contolini , Ronald G. Musket , Anthony F. Bernhardt
IPC分类号： C25D7/12 , C25D5/02
CPC分类号： C25D7/12
摘要： A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.
摘要翻译：一种制造纳米丝场发射器件的方法。该方法能够形成高纵横比，用于场致发射显示器的电镀纳米丝结构器件，其中通孔形成在电介质层中，并且与电介质层顶部的栅极金属结构中的通孔自对准。电介质层中通孔的理想直径约为50-200nm，纵横比为5-10。在一个实施例中，在电介质层中形成通孔之后，栅极金属被钝化，之后必要时在通孔的底部沉积电镀增强层。然后将纳米丝电镀在通孔中，随后除去栅极钝化层，回蚀电介质，并使纳米丝的锐化。硬掩模层可以沉积在栅极金属的顶部上，并在纳米丝的电镀之后去除。

2. 发明授权

US6033583A Vapor etching of nuclear tracks in dielectric materials 失效
标题翻译：电介质材料中核磁道的蒸气蚀刻
公开(公告)号：US6033583A
公开(公告)日：2000-03-07
申请号：US851258
申请日：1997-05-05
申请人： Ronald G. Musket , John D. Porter , James M. Yoshiyama , Robert J. Contolini
发明人： Ronald G. Musket , John D. Porter , James M. Yoshiyama , Robert J. Contolini
IPC分类号： C03C15/00 , C03C17/34 , C03C21/00
CPC分类号： C03C17/3417 , C03C15/00 , C03C17/3482 , C03C2218/33
摘要： A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant. The 20-1000 nm diameter holes resulting from the vapor etching process can be useful as molds for electroplating nanometer-sized filaments, etching gate cavities for deposition of nano-cones, developing high-aspect ratio holes in trackable resists, and as filters for a variety of molecular-sized particles in virtually any liquid or gas by selecting the dielectric material that is compatible with the liquid or gas of interest.
摘要翻译：用于产生高纵横比（即，远大于直径的长度）的电介质材料中的核轨道的蒸汽蚀刻，已经暴露于高能原子粒子的电介质材料中的孤立的圆柱形孔。该方法包括清洁被跟踪材料的表面并将清洁的表面暴露于合适蚀刻剂的蒸汽。独立控制蒸汽和跟踪材料的温度提供了单独改变潜在轨道区域和非轨道材料的蚀刻速率的手段。通常，跟踪区域以比非跟踪区域更大的速率蚀刻。此外，通过随后在液体蚀刻剂中浸渍，可以使蒸气蚀刻的孔扩大和平滑。由气相蚀刻工艺产生的20-1000nm直径的孔可用作用于电镀纳米尺寸丝的模具，用于沉积纳米锥体的蚀刻门腔，在可追踪抗蚀剂中显影高纵横比孔，以及用于通过选择与感兴趣的液体或气体相容的电介质材料，实际上任何液体或气体中的各种分子大小的颗粒。

3. 发明授权

US5256565A Electrochemical planarization 失效
标题翻译：电化学平面化
公开(公告)号：US5256565A
公开(公告)日：1993-10-26
申请号：US348982
申请日：1989-05-08
申请人： Anthony F. Bernhardt , Robert J. Contolini
发明人： Anthony F. Bernhardt , Robert J. Contolini
IPC分类号： H01L21/28 , C23C18/31 , H01L21/3063 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L21/465
CPC分类号： H01L21/7684 , H01L21/32115
摘要： In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
摘要翻译：在用于制造用于集成电路结构的平坦化薄膜金属互连件的工艺中，通过电抛光，离子铣削或其它程序将平坦化金属层回蚀刻到下面的介电层。电抛光将处理时间从几小时缩短到几分钟，并允许批量处理多个晶圆。蚀刻后的平坦化薄膜互连与电介质层齐平。

4. 发明授权

US5096550A Method and apparatus for spatially uniform electropolishing and electrolytic etching 失效
标题翻译：用于空间均匀电解和电解蚀刻的方法和装置
公开(公告)号：US5096550A
公开(公告)日：1992-03-17
申请号：US597225
申请日：1990-10-15
申请人： Steven T. Mayer , Robert J. Contolini , Anthony F. Bernhardt
发明人： Steven T. Mayer , Robert J. Contolini , Anthony F. Bernhardt
IPC分类号： C25F3/02 , C25F3/16 , C25F7/00
CPC分类号： C25F7/00 , C25F3/02 , C25F3/16 , Y10S204/07
摘要： In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.
摘要翻译：在电解抛光或电解蚀刻装置中，阳极与阴极分离，以防止气泡传输到阳极，并通过固体非导电阳极 - 阴极屏障在阳极处产生均匀的电流分布。阳极延伸到屏障的顶部，阴极在屏障外。形成在阴极底部的阴极底部的虚拟阴极孔允许电流流动，同时防止气泡输送。阳极可旋转并水平定向朝下。扩展阳极通过将工件安装在将电解抛光或蚀刻区域延伸超过工件边缘的保持器中形成，以减少工件的边缘效应。参考电极控制电池电压。端点检测和电流切断停止抛光。可以快速进行空间均匀的抛光或蚀刻。

5. 发明授权

US5658832A Method of forming a spacer for field emission flat panel displays 失效
标题翻译：形成用于场致发射平板显示器的间隔件的方法
公开(公告)号：US5658832A
公开(公告)日：1997-08-19
申请号：US324052
申请日：1994-10-17
申请人： Anthony F. Bernhardt , Robert J. Contolini
发明人： Anthony F. Bernhardt , Robert J. Contolini
IPC分类号： H01J9/18 , H01J9/24 , H01J9/00
CPC分类号： H01J9/242 , H01J2329/00 , H01J2329/8625 , H01J2329/864
摘要： Spacers for applications such as field emission flat panel displays and vacuum microelectronics, and which involves the application of aerogel/xerogel technology to the formation of the spacer. In a preferred approach the method uses a mold and mold release agent wherein the gel precursor is a liquid which can be applied to the mold filling holes which expose the substrate (either the baseplate or the faceplate). A release agent is applied to the mold prior to precursor application to ease removal of the mold after formation of the dielectric spacer. The shrinkage of the gel during solvent extraction also improves mold removal. The final spacer material is a good dielectric, such as silica, secured to the substrate.
摘要翻译：用于场致发射平板显示器和真空微电子等应用的间隔器，其涉及将气凝胶/干凝胶技术应用于间隔物的形成。在优选的方法中，该方法使用模具和脱模剂，其中凝胶前体是可以施加到暴露基底（基板或面板）的模具填充孔的液体。在前体施用之前将脱模剂施加到模具以便在形成介电隔离物之后容易地移除模具。溶剂萃取过程中凝胶的收缩也提高了模具去除率。最终的间隔材料是固定到基底上的良好的电介质，例如二氧化硅。

6. 发明授权

US5653019A Repairable chip bonding/interconnect process 失效
标题翻译：可修复芯片接合/互连过程
公开(公告)号：US5653019A
公开(公告)日：1997-08-05
申请号：US522471
申请日：1995-08-31
申请人： Anthony F. Bernhardt , Robert J. Contolini , Vincent Malba , Robert A. Riddle
发明人： Anthony F. Bernhardt , Robert J. Contolini , Vincent Malba , Robert A. Riddle
IPC分类号： H01L21/58 , H01L21/60 , H01L21/68 , H05K3/34
CPC分类号： H01L24/83 , H01L21/6835 , H01L24/19 , H01L24/24 , H01L24/29 , H01L24/82 , H01L2221/6835 , H01L2221/68359 , H01L2224/24051 , H01L2224/24226 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/82001 , H01L2224/83192 , H01L2224/8385 , H01L2924/01006 , H01L2924/01011 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/19042 , Y10T29/49144
摘要： A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
摘要翻译：可修复的片对板互连过程，可解决多芯片模块中的成本和可测试性问题。该工艺可以使用牺牲衬底技术进行，涉及激光加工。该过程避免了以前的方法中遇到的固化/溶剂进化问题，以及解决先前的电镀问题和对圆角的要求。对于可修复的高速芯片到板连接，传输线可以从芯片接合焊盘的芯片侧面形成，结束于芯片底部的鸥翼，用于随后的焊料。

7. 发明授权

US06261961B1 Adhesion layer for etching of tracks in nuclear trackable materials 失效
标题翻译：用于蚀刻核可追踪材料中的轨道的粘附层
公开(公告)号：US06261961B1
公开(公告)日：2001-07-17
申请号：US09258917
申请日：1999-03-01
申请人： Jeffrey D. Morse , Robert J. Contolini
发明人： Jeffrey D. Morse , Robert J. Contolini
IPC分类号： H01L21311
CPC分类号： H01L21/32139
摘要： A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO2), silicon nitride (SiNx), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.
摘要翻译：在核可追溯材料如聚碳酸酯（LEXAN）中形成宽度为100-200nm的核轨道的方法，而不会引起LEXAN的分层。该方法利用具有惰性氧化物的粘合膜，其允许轨道被充分地扩大到> 200nm，而不会使核可追踪材料分层。粘合膜可以由诸如二氧化硅（SiO 2），氮化硅（SiN x）和氧化铝（SiO 2）等具有稳定表面的电介质组成的诸如Cr，Ni，Au，Pt或Ti的金属组成， AlO）。粘附膜可以沉积在栅极金属层的顶部，或者如果粘附膜的性质足够，则可以将其用作栅极层。通过标准技术如溅射或蒸发来实现粘附膜的沉积。

8. 发明授权

US06193870B1 Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices 失效
标题翻译：使用硬掩模通过纳米丝场发射器件形成栅极和电介质
公开(公告)号：US06193870B1
公开(公告)日：2001-02-27
申请号：US08847085
申请日：1997-05-01
申请人： Jeffrey D. Morse , Robert J. Contolini
发明人： Jeffrey D. Morse , Robert J. Contolini
IPC分类号： C25D502
CPC分类号： H01J9/025 , C25D1/04 , H01L21/0332 , H01L21/31116 , H01L21/31144
摘要： A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.
摘要翻译：一种制造纳米丝场发射器件的方法，其中电介质层中的通孔与位于介电层顶部的栅极金属通孔结构自对准。通过使用位于栅极金属层顶部的硬掩模层，对栅极金属层的蚀刻化学物质是惰性的，并且其中通过可追踪材料中蚀刻的核磁道的图案形成通孔，通孔是由硬掩模形成将消除电介质通孔蚀刻期间栅极金属层的任何侵蚀。此外，如果需要的话，硬掩模层将保护栅极金属层，同时栅极结构从电介质通孔的边缘被回蚀。该方法提供了对纳米丝在电介质通孔中的电镀和纳米丝的锐化的更大的公差。

9. 发明授权

US06162344A Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权
标题翻译：使用可变电流和质量传递电镀半导体晶片以获得均匀的镀层的方法
公开(公告)号：US06162344A
公开(公告)日：2000-12-19
申请号：US393226
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
IPC分类号： C25D5/18 , C25D7/12 , C25D5/00
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译：在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。

10. 发明授权

US6110346A Method of electroplating semicoductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权
标题翻译：使用可变电流和质量传递电镀半导体晶片的方法以获得均匀的镀层
公开(公告)号：US6110346A
公开(公告)日：2000-08-29
申请号：US393848
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
IPC分类号： C25D5/18 , C25D7/12 , C25D5/00 , C25D5/16 , C25D9/04
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译：在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。

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