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1. 发明申请

US20130339955A1 SR-IOV FAILOVER & AGGREGATION CONTROL SYSTEM TO ENSURE WITHIN-PHYSICAL-PORT VEB LOOPBACK 有权
标题翻译： SR-IOV故障排除和集成控制系统，以确保物理端口VEB环回
公开(公告)号：US20130339955A1
公开(公告)日：2013-12-19
申请号：US13977606
申请日：2012-06-08
申请人： Jeff Prawer , James R. Hearn , Waseem Ahmad
发明人： Jeff Prawer , James R. Hearn , Waseem Ahmad
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F2009/45595
摘要： Methods, apparatus and systems for effecting Virtual Machine (VM) platform communication loopback and enabling user initiated network port failover. Network communications in platforms employing VMs and having multiple network ports accessible to the VMs are configured to be routed such that communications between VMs in the platform are looped back within the platform, thus not require routing through an external switch. This is facilitated via an Intelligent Channel Bonding Driver that dynamically enforces inter-VM traffic to ensure internal loopback within the same physical port. In another aspect, a user is enabled to initiate failover of a network port on a platform employing a Virtual Machine Manager and a plurality of VMs, wherein updated configuration information is sent to disable Virtual Function (VF) drivers associated with the network port.
摘要翻译：用于实现虚拟机（VM）平台通信环回和启用用户启动的网络端口故障转移的方法，设备和系统。配置使用虚拟机并具有VM可访问的多个网络端口的平台中的网络通信被配置为路由，使得平台中的VM之间的通信环回到平台内，因此不需要通过外部交换机进行路由。这通过智能通道绑定驱动程序来实现，该驱动程序动态地实施VM间流量，以确保同一物理端口内的内部环回。在另一方面，用户能够启动使用虚拟机管理器和多个虚拟机的平台上的网络端口的故障转移，其中更新的配置信息被发送以禁用与网络端口相关联的虚拟功能（VF）驱动器。

2. 发明授权

US09600309B2 SR-IOV failover and aggregation control system to ensure within-physical-port VEB loopback 有权
公开(公告)号：US09600309B2
公开(公告)日：2017-03-21
申请号：US13977606
申请日：2012-06-08
申请人： Jeff Prawer , James R. Hearn , Waseem Ahmad
发明人： Jeff Prawer , James R. Hearn , Waseem Ahmad
IPC分类号： G06F15/173 , G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F2009/45595
摘要： Methods, apparatus and systems for effecting Virtual Machine (VM) platform communication loopback and enabling user initiated network port failover. Network communications in platforms employing VMs and having multiple network ports accessible to the VMs are configured to be routed such that communications between VMs in the platform are looped back within the platform, thus not require routing through an external switch. This is facilitated via an Intelligent Channel Bonding Driver that dynamically enforces inter-VM traffic to ensure internal loopback within the same physical port. In another aspect, a user is enabled to initiate failover of a network port on a platform employing a Virtual Machine Manager and a plurality of VMs, wherein updated configuration information is sent to disable Virtual Function (VF) drivers associated with the network port.

3. 发明申请

US20100141340A1 METHOD AND APPARATUS FOR A HIGH BANDWIDTH AMPLIFIER WITH WIDE BAND PEAKING 有权
标题翻译：具有宽带扬声器的高带宽放大器的方法和装置
公开(公告)号：US20100141340A1
公开(公告)日：2010-06-10
申请号：US12327865
申请日：2008-12-04
申请人： Dawei Huang , Arif Amin , Waseem Ahmad , Rajesh Kumar , Venkatesh Arunachalam
发明人： Dawei Huang , Arif Amin , Waseem Ahmad , Rajesh Kumar , Venkatesh Arunachalam
IPC分类号： H03F3/45 , H03G3/30 , H04L25/49
CPC分类号： H03G1/0029 , H03F3/45197 , H03F2200/411 , H03F2200/453 , H03F2203/45491 , H03F2203/45492 , H03F2203/45494 , H03F2203/45511 , H03F2203/45652 , H03F2203/45702 , H04L25/0272
摘要： A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.
摘要翻译：已经设计了一个两级全差分放大器，它与TX-FIR一起作为低频的线性均衡器工作，不被TX-FIR覆盖，并且还作为较高频率的线性放大器，它们被均衡 TX-FIR。作为频率响应的放大器，其不会衰减信号频率小于波特率的二十分之一，从而使波峰率的二分之一到十分之一的区域产生增益峰值，并将平坦的峰值增益保持在一半以上的波特率。频率响应曲线（如直流增益，最大增益和零频率）的不同方面是完全可编程的。此外，差分放大器是从低功耗和工艺，电压和温度不敏感的频率响应设计的。

4. 发明授权

US08751518B1 Fixed phrase detection for search 有权
标题翻译：用于搜索的固定短语检测
公开(公告)号：US08751518B1
公开(公告)日：2014-06-10
申请号：US13465884
申请日：2012-05-07
申请人： Waseem Ahmad , Deepak Jain
发明人： Waseem Ahmad , Deepak Jain
IPC分类号： G06F17/30
CPC分类号： G06F17/30598 , G06F17/30616 , G06F17/30864
摘要： A set of search requests may be analyzed to detect fixed phrases suitable for inclusion in a search index. Sets of candidate phrases may be identified among the search requests. Fixed phrases may be detected among the candidate phrases using statistical techniques, for example, by identifying phrases having a relatively high pointwise mutual information (PMI) with respect to component keywords. Fixed phrase detection may include keyword and/or phrase clustering. Clusters may correspond to topics defined using a latent Dirichlet allocation (LDA) procedure. Fixed phrase detection may include identifying phrases having relatively high PMI within particular clusters.
摘要翻译：可以分析一组搜索请求以检测适合于包括在搜索索引中的固定短语。可以在搜索请求之间识别候选短语的集合。使用统计技术可以在候选短语中检测固定短语，例如通过识别关于组件关键词具有相对较高的点互信息（PMI）的短语。固定短语检测可以包括关键字和/或短语聚类。群集可能对应于使用潜在的Dirichlet分配（LDA）过程定义的主题。固定短语检测可以包括识别在特定簇内具有相对较高PMI的短语。

5. 发明授权

US08243866B2 Analog baud rate clock and data recovery 有权
标题翻译：模拟波特率时钟和数据恢复
公开(公告)号：US08243866B2
公开(公告)日：2012-08-14
申请号：US12116329
申请日：2008-05-07
申请人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
发明人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
IPC分类号： H04L7/00 , H04L27/06
CPC分类号： H04L7/0062
摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.
摘要翻译：模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。从第一和第二电位定时误差信号导出期望的定时误差信号。所需的定时误差信号用于确定信号采样是早还是晚。

6. 发明授权

US08452829B2 Real-time optimization of TX FIR filter for high-speed data communication 有权
标题翻译：实时优化TX FIR滤波器，实现高速数据通信
公开(公告)号：US08452829B2
公开(公告)日：2013-05-28
申请号：US12144610
申请日：2008-06-23
申请人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
发明人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
IPC分类号： G06F17/10
CPC分类号： H04L25/03343 , H04L7/0058
摘要： A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
摘要翻译：定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

7. 发明授权

US08176067B1 Fixed phrase detection for search 有权
标题翻译：用于搜索的固定短语检测
公开(公告)号：US08176067B1
公开(公告)日：2012-05-08
申请号：US12712081
申请日：2010-02-24
申请人： Waseem Ahmad , Deepak Jain
发明人： Waseem Ahmad , Deepak Jain
IPC分类号： G06F17/30
CPC分类号： G06F17/30598 , G06F17/30616 , G06F17/30864
摘要： A set of search requests may be analyzed to detect fixed phrases suitable for inclusion in a search index. Sets of candidate phrases may be identified among the search requests. Fixed phrases may be detected among the candidate phrases using statistical techniques, for example, by identifying phrases having a relatively high pointwise mutual information (PMI) with respect to component keywords. Fixed phrase detection may include keyword and/or phrase clustering. Clusters may correspond to topics defined using a latent Dirichlet allocation (LDA) procedure. Fixed phrase detection may include identifying phrases having relatively high PMI within particular clusters.
摘要翻译：可以分析一组搜索请求以检测适合于包括在搜索索引中的固定短语。可以在搜索请求之间识别候选短语的集合。使用统计技术可以在候选短语中检测固定短语，例如通过识别关于组件关键词具有相对较高的点互信息（PMI）的短语。固定短语检测可以包括关键字和/或短语聚类。群集可能对应于使用潜在的Dirichlet分配（LDA）过程定义的主题。固定短语检测可以包括识别在特定簇内具有相对较高PMI的短语。

8. 发明授权

US06397158B1 Method for determining capacitance values for quieting noisy power conductors 有权
标题翻译：确定静音电力导体电容值的方法
公开(公告)号：US06397158B1
公开(公告)日：2002-05-28
申请号：US09303103
申请日：1999-04-29
申请人： Waseem Ahmad , Kazi M. Hassan
发明人： Waseem Ahmad , Kazi M. Hassan
IPC分类号： G01R3108
CPC分类号： G01R27/2605
摘要： A method for determining the value of at least one capacitance required to be placed in a conductive path on a printed circuit board is disclosed. The method includes preparing a desired signal spectrum for the conductive path, preparing an actual signal spectrum for the conductive path, and then comparing the actual signal spectrum against the desired signal spectrum to determine where any out of tolerance conditions exist. If the actual signal spectrum is in amplitude versus time form, the method further includes performing, for each time having a voltage which is higher than the maximum voltage allowed on the conductive path, a fourier transform on the amplitude versus time data. Following the optional conversion, the method proceeds with the determination of at least one frequency having an amplitude which significantly contributes to the out of tolerance condition, and computing, for the one or more frequencies contributing to the out of tolerance condition, a value of capacitance which would diminish the amplitude at that frequency to a value which is within tolerance.
摘要翻译：公开了一种用于确定需要放置在印刷电路板上的导电路径中的至少一个电容的值的方法。该方法包括制备用于导电路径的期望信号频谱，准备用于导电路径的实际信号频谱，然后将实际信号频谱与期望信号频谱进行比较，以确定存在任何超出公差条件的位置。如果实际的信号频谱是以幅度对时间的形式，则该方法还包括对于具有高于导电路径上允许的最大电压的电压的每一次对幅度对时间数据进行傅里叶变换。在可选转换之后，该方法继续确定具有显着有助于超出公差条件的幅度的至少一个频率，并且对于有助于超出公差条件的一个或多个频率，计算电容值这将使该频率处的幅度减小到公差内的值。

9. 发明授权

US6150843A Five volt tolerant I/O buffer 失效
标题翻译：五伏容忍I / O缓冲器
公开(公告)号：US6150843A
公开(公告)日：2000-11-21
申请号：US15328
申请日：1998-01-29
申请人： James D. Shiffer , Waseem Ahmad
发明人： James D. Shiffer , Waseem Ahmad
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/00315
摘要： A 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage, for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current flow into the power supply terminal when the pad is coupled to a voltage greater than the predetermined power supply voltage. A driver transistor of a first type is formed within a diffusion well and is coupled to the predetermined power supply voltage and to the pad. First and second terminals of a protection transistor are coupled to respective ones of the predetermined power supply voltage and the diffusion well. Circuitry is provided for, when the output enable signal is active, turning on the protection transistor so as to couple the predetermined power supply voltage to the diffusion well, regardless of a voltage level of the pad. A single protection transistor is sufficient to prevent current leakage through the parasitic PN diode.
摘要翻译： 5伏容限I / O缓冲电路被耦合到预定电源电压的电源端子，用于根据输入信号和输出使能信号将I / O焊盘驱动到逻辑状态。当焊盘耦合到大于预定电源电压的电压时，I / O缓冲电路使流入电源端的电流最小化。第一类型的驱动晶体管形成在扩散阱内并且耦合到预定的电源电压和焊盘。保护晶体管的第一和第二端子耦合到预定电源电压和扩散阱中的相应的一个。提供电路，当输出使能信号有效时，不管垫的电压电平如何，导通保护晶体管以将预定的电源电压耦合到扩散阱。单个保护晶体管足以防止通过寄生PN二极管的电流泄漏。

10. 发明授权

US5864243A Buffer and method for transferring data therein 失效
标题翻译：用于在其中传送数据的缓冲器和方法
公开(公告)号：US5864243A
公开(公告)日：1999-01-26
申请号：US715457
申请日：1996-09-18
申请人： Deng-Yuan David Chen , Waseem Ahmad
发明人： Deng-Yuan David Chen , Waseem Ahmad
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/00315
摘要： A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.
摘要翻译：提供了具有降低功耗的混合电压兼容缓冲器。根据本发明的缓冲器的一个实施例包括：数据输入，被配置为接收输出数据信号; 数据接口，被配置为与焊盘互连耦合; 与所述数据接口耦合并被配置为向其施加输出数据信号的输出驱动器; 以及在所述数据输入和所述输出驱动器之间的数据控制器，所述数据控制器被配置为向所述输出驱动器施加基本上相等电压的多个控制信号，以响应于经由所述数据输入接收到的输出数据信号来控制其操作。本发明还提供了一种在缓冲器内传送数据的方法。

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