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1. 发明授权

US08536043B2 Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge 有权
标题翻译：使用n + Ge的低温金属诱导结晶降低了III-V MOSFET的S / D接触电阻
公开(公告)号：US08536043B2
公开(公告)日：2013-09-17
申请号：US13017127
申请日：2011-01-31
申请人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
发明人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
IPC分类号： H01L21/28
CPC分类号： H01L29/20 , H01L21/26513 , H01L21/28575 , H01L29/0847 , H01L29/267 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.
摘要翻译：本发明的实施例提供一种制造电接触的方法。该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域，通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上覆金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层，将无定形锗层转化为结晶锗层并激活注入的掺杂剂。电接触可以是晶体管的源极或漏极接触。

2. 发明申请

US20120193687A1 REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF n+ Ge 有权
标题翻译：使用n + Ge低温金属诱导结晶的III-V MOSFET的降低的S / D接触电阻
公开(公告)号：US20120193687A1
公开(公告)日：2012-08-02
申请号：US13017127
申请日：2011-01-31
申请人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
发明人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/20 , H01L21/26513 , H01L21/28575 , H01L29/0847 , H01L29/267 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.
摘要翻译：本发明的实施例提供一种制造电接触的方法。该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域，通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上层金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层，将无定形锗层转化为结晶锗层并激活注入的掺杂剂。电接触可以是晶体管的源极或漏极接触。

3. 发明申请

US20120318338A1 NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS 审中-公开
公开(公告)号：US20120318338A1
公开(公告)日：2012-12-20
申请号：US13599577
申请日：2012-08-30
申请人： Keith E. Fogel , Jeehwan Kim , Jae-Woong Nah , Devendra K. Sadana , Kuen-Ting Shiu
发明人： Keith E. Fogel , Jeehwan Kim , Jae-Woong Nah , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L31/0236 , H01L31/076 , H01L31/075
CPC分类号： H01L31/1804 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/0352 , H01L31/035227 , Y02E10/50
摘要： A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

4. 发明申请

US20120318342A1 UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS 有权
标题翻译：用于高效太阳能电池的均匀分布自组装式锥形支架
公开(公告)号：US20120318342A1
公开(公告)日：2012-12-20
申请号：US13161163
申请日：2011-06-15
申请人： CHRISTOS DIMITRAKOPOULOS , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
发明人： CHRISTOS DIMITRAKOPOULOS , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0689 , G06F11/0727 , G06F11/1076 , G06F12/02 , H01L31/02366 , H04L67/1002 , H04W8/04 , H04W8/065 , Y02E10/50
摘要： A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
摘要翻译：一种制造光伏器件的方法包括在基片上涂布二嵌段共聚物层，并从二嵌段共聚物层除去第一聚合物材料以形成多个分布孔。图案形成层沉积在二嵌段共聚物层的剩余表面上和与基材接触的孔中。剥离二嵌段共聚物层，使图案形成层的一部分与基板保持接触。使用图案形成层蚀刻衬底以保护衬底的部分以在衬底中形成柱，使得柱在光伏器件中提供辐射吸收结构。

5. 发明申请

US20120187505A1 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation 审中-公开
标题翻译：自对准III-V MOSFET制造，具有原位III-V外延和原位金属外延和接触形成
公开(公告)号：US20120187505A1
公开(公告)日：2012-07-26
申请号：US13013206
申请日：2011-01-25
申请人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/26546 , H01L21/28575 , H01L21/3245 , H01L29/0847 , H01L29/201 , H01L29/207 , H01L29/41783 , H01L29/452 , H01L29/66446 , H01L29/66477 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.
摘要翻译：一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源/漏区上生长金属接触。还公开了晶体管和计算机程序产品。

6. 发明授权

US08822317B2 Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact 有权
标题翻译：自对准III-V MOSFET扩散区和硅化物样合金接触
公开(公告)号：US08822317B2
公开(公告)日：2014-09-02
申请号：US13603739
申请日：2012-09-05
申请人： Cheng-Wei Cheng , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
发明人： Cheng-Wei Cheng , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L21/336
CPC分类号： H01L21/2258 , H01L21/246 , H01L21/28575 , H01L29/41775 , H01L29/452 , H01L29/517 , H01L29/66522
摘要： A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.
摘要翻译：金属氧化物半导体场效应晶体管及其形成方法包括在与栅极叠层相邻的衬底上的曝光部分，在栅极堆叠上形成掺杂剂层，并在暴露并退火掺杂剂层驱动的部分中与衬底接触掺杂到衬底中以在衬底中形成自对准掺杂剂区域。去除掺杂剂层。在栅极叠层上沉积含金属层，并在暴露部分与衬底接触。对含金属层进行退火以将金属驱动到衬底中，以在掺杂区域内的衬底中形成的金属合金中形成自对准接触区域。然后去除金属层。

7. 发明授权

US08628996B2 Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells 有权
标题翻译：用于高效太阳能电池的均匀分布的自组装锥形柱
公开(公告)号：US08628996B2
公开(公告)日：2014-01-14
申请号：US13161163
申请日：2011-06-15
申请人： Christos Dimitrakopoulos , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
发明人： Christos Dimitrakopoulos , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L31/0232
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0689 , G06F11/0727 , G06F11/1076 , G06F12/02 , H01L31/02366 , H04L67/1002 , H04W8/04 , H04W8/065 , Y02E10/50
摘要： A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
摘要翻译：一种制造光伏器件的方法包括在基片上涂布二嵌段共聚物层，并从二嵌段共聚物层除去第一聚合物材料以形成多个分布孔。图案形成层沉积在二嵌段共聚物层的剩余表面上和与基材接触的孔中。剥离二嵌段共聚物层，使图案形成层的一部分与基板保持接触。使用图案形成层蚀刻衬底以保护衬底的部分以在衬底中形成柱，使得柱在光伏器件中提供辐射吸收结构。

8. 发明申请

US20130001659A1 SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT 有权
标题翻译：自对准III-V MOSFET扩散区和类硅合金接触
公开(公告)号：US20130001659A1
公开(公告)日：2013-01-03
申请号：US13603739
申请日：2012-09-05
申请人： Cheng-Wei Cheng , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
发明人： Cheng-Wei Cheng , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L29/78
CPC分类号： H01L21/2258 , H01L21/246 , H01L21/28575 , H01L29/41775 , H01L29/452 , H01L29/517 , H01L29/66522
摘要： A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.
摘要翻译：金属氧化物半导体场效应晶体管及其形成方法包括在与栅极叠层相邻的衬底上的曝光部分，在栅极叠层上形成掺杂剂层，并在暴露并退火掺杂剂层驱动的部分中与衬底接触掺杂到衬底中以在衬底中形成自对准掺杂剂区域。去除掺杂剂层。在栅极叠层上沉积含金属层，并在暴露部分与衬底接触。对含金属层进行退火以将金属驱动到衬底中，以在掺杂区域内的衬底中形成的金属合金中形成自对准接触区域。然后去除金属层。

9. 发明申请

US20120285520A1 WAFER BONDED SOLAR CELLS AND FABRICATION METHODS 有权
标题翻译： WAFER BONDED太阳能电池和制造方法
公开(公告)号：US20120285520A1
公开(公告)日：2012-11-15
申请号：US13107371
申请日：2011-05-13
申请人： Stephen W. Bedell , Cheng-Wei Cheng , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
发明人： Stephen W. Bedell , Cheng-Wei Cheng , Jeehwan Kim , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
IPC分类号： H01L31/06 , H01L31/18
CPC分类号： H01L31/0687 , H01L31/18 , Y02E10/544
摘要： A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
摘要翻译：光伏器件和制造方法包括多结电池，每个电池具有彼此独立生长且包括不同带隙能量的材料。接口设置在单元之间并被配置为晶片结合单元，其中单元被配置为相邻而不考虑晶格失配。

10. 发明申请

US20120060905A1 NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS 有权
标题翻译：通过使用NANODOTS生产的纳米线
公开(公告)号：US20120060905A1
公开(公告)日：2012-03-15
申请号：US12879209
申请日：2010-09-10
申请人： KEITH E. FOGEL , Jeehwan Kim , Jae-Woong Nah , Devendra K. Sadana , Kuen-Ting Shiu
发明人： KEITH E. FOGEL , Jeehwan Kim , Jae-Woong Nah , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L31/04 , H01L31/18
CPC分类号： H01L31/035227 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/0352 , H01L31/1804 , Y02E10/50
摘要： A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
摘要翻译：光电器件和方法包括在衬底层上沉积金属膜。金属膜退火以在基底层上形成金属膜岛。使用岛作为蚀刻掩模蚀刻衬底层，以在衬底层中形成柱。

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