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1. 发明授权

US07242621B2 Floating-gate MOS transistor with double control gate 有权
标题翻译：具有双控制栅极的浮栅MOS晶体管
公开(公告)号：US07242621B2
公开(公告)日：2007-07-10
申请号：US11155306
申请日：2005-06-17
申请人： Jean-Michel Mirabel , Arnaud Regnier , Rachid Bouchakour , Romain Laffont , Pascal Masson
发明人： Jean-Michel Mirabel , Arnaud Regnier , Rachid Bouchakour , Romain Laffont , Pascal Masson
IPC分类号： G11C16/04
CPC分类号： H01L29/7883 , H01L29/42328
摘要： The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.
摘要翻译：本发明涉及一种浮栅MOS晶体管，其包括注入到硅衬底中的漏极和源极区域，在漏极和源极区域之间延伸的沟道，隧道氧化物，浮置栅极，栅极氧化物和控制栅极，其根据到确定的门长度。根据本发明，控制栅极包括并排布置并由电绝缘材料隔开的小栅极和大栅极。应用于无存取晶体管的存储器单元的生产，并且实现具有降低隧道氧化物的电应力的擦除程序方法。

2. 发明申请

US20070069278A1 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US20070069278A1
公开(公告)日：2007-03-29
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

3. 发明申请

US20050286303A1 Floating-gate MOS transistor with double control gate 有权
标题翻译：具有双控制栅极的浮栅MOS晶体管
公开(公告)号：US20050286303A1
公开(公告)日：2005-12-29
申请号：US11155306
申请日：2005-06-17
申请人： Jean-Michel Mirabel , Arnaud Regnier , Rachid Bouchakour , Romain Laffont , Pascal Masson
发明人： Jean-Michel Mirabel , Arnaud Regnier , Rachid Bouchakour , Romain Laffont , Pascal Masson
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788 , G11C11/34
CPC分类号： H01L29/7883 , H01L29/42328
摘要： The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.
摘要翻译：本发明涉及一种浮栅MOS晶体管，其包括注入到硅衬底中的漏极和源极区域，在漏极和源极区域之间延伸的沟道，隧道氧化物，浮置栅极，栅极氧化物和控制栅极，其根据到确定的门长度。根据本发明，控制栅极包括并排布置并由电绝缘材料隔开的小栅极和大栅极。应用于无存取晶体管的存储器单元的生产，并且实现具有降低隧道氧化物的电应力的擦除程序方法。

4. 发明授权

US07675106B2 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US07675106B2
公开(公告)日：2010-03-09
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/423
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

5. 发明授权

US08729668B2 Adjustable resistor 有权
标题翻译：可调电阻
公开(公告)号：US08729668B2
公开(公告)日：2014-05-20
申请号：US13552973
申请日：2012-07-19
申请人： Pascal Fornara , Arnaud Regnier
发明人： Pascal Fornara , Arnaud Regnier
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/11526 , H01L27/11531
摘要： An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
摘要翻译：一种形成在基板的第一绝缘层上的可调电阻器，包括：第一多晶硅层，其被第一厚度的第二绝缘层覆盖，除了第一多晶硅层被第二厚度的薄绝缘层覆盖的区域之外小于第一厚度; 覆盖所述第二绝缘层和所述薄绝缘体层的第二多晶硅层; 在所述第二绝缘层的每一侧上与所述第二绝缘层相距一定距离处的第一和第二导电通孔提供对所述第一多晶硅层上的所述电阻器的端子的访问; 以及第三导电通孔，其提供对所述第二多晶硅层上的接触区域的接近。

6. 发明申请

US20130032926A1 ADJUSTABLE RESISTOR 有权
标题翻译：可调电阻
公开(公告)号：US20130032926A1
公开(公告)日：2013-02-07
申请号：US13552973
申请日：2012-07-19
申请人： Pascal FORNARA , Arnaud Regnier
发明人： Pascal FORNARA , Arnaud Regnier
IPC分类号： H01L27/08
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/11526 , H01L27/11531
摘要： An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
摘要翻译：一种形成在基板的第一绝缘层上的可调电阻器，包括：第一多晶硅层，其被第一厚度的第二绝缘层覆盖，除了第一多晶硅层被第二厚度的薄绝缘层覆盖的区域之外小于第一厚度; 覆盖所述第二绝缘层和所述薄绝缘体层的第二多晶硅层; 在所述第二绝缘层的每一侧上与所述第二绝缘层相距一定距离处的第一和第二导电通孔提供对所述第一多晶硅层上的所述电阻器的端子的访问; 以及第三导电通孔，其提供对所述第二多晶硅层上的接触区域的接近。

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