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1. 发明授权

US4504901A Communication line adapter for use with a communications controller 失效
标题翻译：用于通讯控制器的通讯线适配器
公开(公告)号：US4504901A
公开(公告)日：1985-03-12
申请号：US300846
申请日：1981-09-10
申请人： Jean L. Calvignac , Rene R. Castel
发明人： Jean L. Calvignac , Rene R. Castel
IPC分类号： H04L29/04 , G06F13/00 , G06F13/38 , G06F3/04
CPC分类号： G06F13/385
摘要： A line adapter for permitting the transfer of information between terminals and a bus connected to the central control unit CCU of a communications controller. The line adapter includes a microprocessor associated with a control memory and a scanner. A random access memory is split into zones, one zone being assigned to each line. During an initiating phase, the zones are personalized under the control of the microcode by sending initiating parameters (which are characteristics of the lines) to the memory, through an asynchronous path bus and external registers. Exchanges of temporarily-stored data between the CCU bus and the lines are carried out through cycle steal operations between the control memory and the random access memory.
摘要翻译：用于允许终端之间的信息传输和连接到通信控制器的中央控制单元CCU的总线的线路适配器。线路适配器包括与控制存储器和扫描器相关联的微处理器。随机访问存储器被分割成区域，一个区域被分配给每一行。在启动阶段，通过将异步路径总线和外部寄存器发送启动参数（它们是线路的特性）到存储器，在微代码的控制下对这些区域进行个性化处理。通过控制存储器和随机存取存储器之间的循环窃取操作来执行在CCU总线和线路之间临时存储的数据的交换。

2. 发明授权

US08942095B2 Identification of QoS classification based on packet attributes 有权
标题翻译：基于分组属性的QoS分类识别
公开(公告)号：US08942095B2
公开(公告)日：2015-01-27
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/54 , H04L12/851 , H04L29/06
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

3. 发明授权

US08867395B2 Accelerating data packet parsing 有权
公开(公告)号：US08867395B2
公开(公告)日：2014-10-21
申请号：US13570343
申请日：2012-08-09
申请人： Francois Abel , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Fabrice J. Verplanken
发明人： Francois Abel , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Fabrice J. Verplanken
IPC分类号： H04L12/741 , G06F9/38 , H04L12/801
CPC分类号： G06F9/3885 , H04L45/74 , H04L47/10
摘要： Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.

4. 发明申请

US20120221928A1 CHECKSUM VERIFICATION ACCELERATOR 有权
标题翻译：检查验证加速器
公开(公告)号：US20120221928A1
公开(公告)日：2012-08-30
申请号：US13466940
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0079 , H04L1/0061 , H04L1/0072
摘要： Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum.
摘要翻译：公开了一种通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法。网络处理器接收数据包：识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。该方法利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。该方法通过将数据包校验和与第二校验和进行比较来验证数据包。

5. 发明申请

US20120147892A1 ANALYSIS OF NETWORK PACKETS USING A GENERATED HASH CODE 审中-公开
标题翻译：使用生成的哈希码对网络分组进行分析
公开(公告)号：US20120147892A1
公开(公告)日：2012-06-14
申请号：US13325597
申请日：2011-12-14
申请人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L45/74 , H04L69/22
摘要： A technique for analyzing network packets includes receiving, by a network processor, a network packet having a packet header including address and control information. A set of bytes are extracted, using the network processor, from the packet header and a set of input bits for generating a hash code are derived, using the network processor, from the set of bytes. Finally, the hash code is generated using the input bits.
摘要翻译：用于分析网络分组的技术包括由网络处理器接收具有包含地址和控制信息的分组报头的网络分组。使用网络处理器从分组报头提取一组字节，并且使用网络处理器从该组字节导出用于生成散列码的一组输入比特。最后，使用输入位生成哈希码。

6. 发明授权

US08122132B2 Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
标题翻译：基于广播信息将作业动态地分配给集群中的处理器的技术
公开(公告)号：US08122132B2
公开(公告)日：2012-02-21
申请号：US12336312
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F13/00
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).
摘要翻译：用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息多个节点中的一个。基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

7. 发明授权

US07929438B2 Scheduler pipeline design for hierarchical link sharing 失效
标题翻译：调度器管道设计用于分层链路共享
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

8. 发明授权

US07844746B2 Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters 有权
标题翻译：访问有效地址并确定有效地址是否与远程耦合的I / O适配器相关联
公开(公告)号：US07844746B2
公开(公告)日：2010-11-30
申请号：US12024695
申请日：2008-02-01
申请人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Edward J. Seminaro
发明人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Edward J. Seminaro
IPC分类号： G06F3/12
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元件模型抽象出I / O设备，使得针对I / O设备的通信可以被分组并通过网络发送。因此，虚拟化平台可以打包用于远程位置的I / O设备的通信，并且在一定距离上发送分组化的通信，而不是必须对库进行呼叫，调用设备驱动器，引脚存储器等。

9. 发明申请

US20100153541A1 TECHNIQUES FOR DYNAMICALLY ASSIGNING JOBS TO PROCESSORS IN A CLUSTER BASED ON PROCESSOR WORKLOAD 有权
标题翻译：基于处理器工作负载的集群中的处理器动态组织工作的技术
公开(公告)号：US20100153541A1
公开(公告)日：2010-06-17
申请号：US12336256
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F15/173
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.
摘要翻译：用于操作高性能计算（HPC）集群的技术包括监视包含在HPC集群中的多个处理器的工作负载。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。基于多个处理器的工作负载，分配给多个处理器中的一个或多个的一个或多个线程被移动到多个处理器中的不同处理器。

10. 发明授权

US07643511B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07643511B2
公开(公告)日：2010-01-05
申请号：US12327761
申请日：2008-12-03
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

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