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1. 发明申请

US20120323542A1 METHOD FOR CALCULATING PARAMETER VALUES OF THIN-FILM TRANSISTOR AND APPARATUS FOR PERFORMING THE METHOD 有权
标题翻译：计算薄膜晶体管参数值的方法及其方法
公开(公告)号：US20120323542A1
公开(公告)日：2012-12-20
申请号：US13481579
申请日：2012-05-25
申请人： Je-Hun LEE , Byung-Du AHN , Sei-Yong PARK , Jun-Hyun PARK , Jae-Woo PARK , Dae-Hwan KIM , Sung-Chul KIM , Yong-Woo JEON
发明人： Je-Hun LEE , Byung-Du AHN , Sei-Yong PARK , Jun-Hyun PARK , Jae-Woo PARK , Dae-Hwan KIM , Sung-Chul KIM , Yong-Woo JEON
IPC分类号： G06G7/62
CPC分类号： G06F17/5036
摘要： A method for calculating values of parameters of a TFT includes calculating a set of simulated current-voltage (I-V) values using state-density-functions over an entire energy band in a band gap of an amorphous semiconductor of the TFT. The method further includes comparing the set of simulated I-V values with a set of measured I-V values of the TFT to determine a value of a parameter of the TFT. The method may further include calculating values of an acceptor state-density-function gA using a set of electrostatic capacity-voltage (C-V) values of the TFT measured according to a frequency. The method may further include determining values of a donor state-density-function gD and values of an interface state-density-function Dit over the entire energy band in the band gap.
摘要翻译：用于计算TFT的参数值的方法包括使用TFT的非晶半导体的带隙中的整个能带上的状态密度函数来计算一组模拟电流 - 电压（I-V）值。所述方法还包括将所述一组模拟I-V值与所述TFT的测量I-V值的集合进行比较，以确定所述TFT的参数的值。该方法还可以包括使用根据频率测量的TFT的一组静电电容电压（C-V）值来计算受主状态密度函数gA的值。该方法还可以包括在带隙中的整个能带上确定施主状态密度函数gD的值和接口状态密度函数Dit的值。

2. 发明申请

US20110284836A1 OXIDE SEMICONDUCTOR THIN-FILM TRANSISTOR 有权
标题翻译：氧化物半导体薄膜晶体管
公开(公告)号：US20110284836A1
公开(公告)日：2011-11-24
申请号：US13080413
申请日：2011-04-05
申请人： Je-Hun LEE , Jae-Woo PARK , Byung-Du AHN , Sei-Yong PARK , Jun-Hyun PARK
发明人： Je-Hun LEE , Jae-Woo PARK , Byung-Du AHN , Sei-Yong PARK , Jun-Hyun PARK
IPC分类号： H01L29/786
CPC分类号： H01L29/45 , H01L29/78618 , H01L29/7869 , H01L29/78696
摘要： A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a gate insulation layer and an oxide semiconductor pattern. The source and drain electrodes include a first metal element with a first oxide formation free energy. The oxide semiconductor pattern has a first surface making contact with the gate insulation layer and a second surface making contact with the source and drain electrodes to be positioned at an opposite side of the first surface. The oxide semiconductor pattern includes an added element having a second oxide formation free energy having an absolute value greater than or equal to an absolute value of the first oxide formation free energy, wherein an amount of the added element included in a portion near the first surface is zero or smaller than an amount of the added element included in a portion near the second surface.
摘要翻译：薄膜晶体管包括栅电极，源电极，漏电极，栅极绝缘层和氧化物半导体图案。源极和漏极包括具有第一氧化物形成自由能的第一金属元件。氧化物半导体图案具有与栅极绝缘层接触的第一表面和与源极和漏极电极接触以与第一表面相对的第二表面。氧化物半导体图案包括具有绝对值大于或等于第一氧化物形成自由能的绝对值的第二氧化物形成自由能的添加元素，其中包括在第一表面附近的部分中的添加元素的量为零或小于包含在靠近第二表面的部分中的添加元素的量。

3. 发明申请

US20120018720A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US20120018720A1
公开(公告)日：2012-01-26
申请号：US13177783
申请日：2011-07-07
申请人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Hye-Young RYU , Young-Joo CHOI
发明人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Hye-Young RYU , Young-Joo CHOI
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L27/124 , H01L29/458
摘要： A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.
摘要翻译：显示基板包括在基底基板上沿第一方向延伸的栅极线，在基底基板上的数据线，并且沿与第一方向交叉的第二方向延伸，栅极线上的栅极绝缘层，薄膜晶体管和像素电极。薄膜晶体管包括栅电极，电极连接栅极线，氧化物半导体图案以及氧化物半导体图案上的源电极和漏电极并彼此间隔开。氧化物半导体图案包括包括氧化铟的第一半导体图案和包含无铟氧化物的第二半导体图案。像素电极与漏电极电连接。

4. 发明申请

US20110292725A1 FLASH MEMORY DEVICE AND SYSTEM WITH PROGRAM SEQUENCER, AND PROGRAMMING METHOD 有权
标题翻译：具有程序序列的FLASH存储器件和系统以及编程方法
公开(公告)号：US20110292725A1
公开(公告)日：2011-12-01
申请号：US13089639
申请日：2011-04-19
申请人： Ki Hwan CHOI , Sung Soo LEE , Jae-Woo PARK , Sang-Hyun JOO
发明人： Ki Hwan CHOI , Sung Soo LEE , Jae-Woo PARK , Sang-Hyun JOO
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3436
摘要： A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program sequence for the LSB and MSB programming operations may be sequential or non-sequential in relation to an order arranged of word lines.
摘要翻译：用于非易失性存储器件的编程方法包括执行编程所有LSB逻辑页的LSB编程操作，并且此后执行MSB编程操作编程所有MSB逻辑页，其中在LSB编程操作期间，所选择的MLC被编程为负的中间程序状态。用于LSB和MSB编程操作的程序序列可以是与字线布置的顺序相关或非顺序的。

5. 发明申请

US20120286259A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：显示基板及其制造方法
公开(公告)号：US20120286259A1
公开(公告)日：2012-11-15
申请号：US13431448
申请日：2012-03-27
申请人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON
发明人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/1288 , H01L29/66969
摘要： Exemplary embodiments of the present invention provide a display substrate including a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode, and an etch stop pattern. The gate electrode may be disposed on a base substrate. The oxide semiconductor pattern may be disposed over the gate electrode. The source electrode may be disposed on the oxide semiconductor pattern. The drain electrode may be disposed on the oxide semiconductor pattern and spaced apart from the source electrode. The etch stop pattern may be disposed over the gate electrode, the etch stop pattern may be overlapping a space between the source electrode and the drain electrode and may include a metal oxide. The reliability of the display substrate may, therefore, be improved.
摘要翻译：本发明的示例性实施例提供了包括栅电极，氧化物半导体图案，源电极，漏电极和蚀刻停止图案的显示基板。栅电极可以设置在基底基板上。氧化物半导体图案可以设置在栅极上。源极可以设置在氧化物半导体图案上。漏极可以设置在氧化物半导体图案上并与源电极间隔开。蚀刻停止图案可以设置在栅电极之上，蚀刻停止图案可以与源电极和漏电极之间的空间重叠，并且可以包括金属氧化物。因此，可以提高显示基板的可靠性。

6. 发明申请

US20120217500A1 WIRING, THIN FILM TRANSISTOR, THIN FILM TRANSISTOR PANEL AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：导线，薄膜晶体管，薄膜晶体管板及其制造方法
公开(公告)号：US20120217500A1
公开(公告)日：2012-08-30
申请号：US13242257
申请日：2011-09-23
申请人： Jae-Woo PARK , Sung-Haeng CHO , Kyong-Sub KIM , Dong-Yeong CHO
发明人： Jae-Woo PARK , Sung-Haeng CHO , Kyong-Sub KIM , Dong-Yeong CHO
IPC分类号： H01L33/08 , H01L23/48 , H01L21/336
CPC分类号： H01L29/45 , H01L29/458 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A thin film transistor includes a gate electrode, a gate insulating layer on the gate electrode, a semiconductor on the gate insulating layer, and a drain electrode and a source electrode on the semiconductor and spaced apart from each other. Each of the drain electrode and the source electrode includes a first metal diffusion preventing layer which prevents diffusion of metal atoms, and a second metal diffusion preventing layer on the first metal diffusion preventing layer. At least one of the first and second metal diffusion preventing layers includes grains in a columnar structure, which are in a direction substantially perpendicular to a lower layer. First grain boundaries of the first metal diffusion preventing layer and second grain boundaries of the second metal diffusion preventing layer are substantially discontinuous in a direction perpendicular to the semiconductor.
摘要翻译：薄膜晶体管包括栅电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体，以及半导体上的间隔开的漏电极和源电极。漏电极和源电极中的每一个包括防止金属原子扩散的第一金属扩散防止层和第一金属扩散防止层上的第二金属扩散防止层。第一和第二金属扩散防止层中的至少一个包括柱状结构中的大致垂直于下层的方向的晶粒。第一金属扩散防止层的第一晶界和第二金属扩散防止层的第二晶界在垂直于半导体的方向上基本上不连续。

7. 发明申请

US20120052420A1 HALF TONE MASK HAVING MULTI-HALF PERMEATION PART AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有多层透气部分的半透明面膜及其制造方法
公开(公告)号：US20120052420A1
公开(公告)日：2012-03-01
申请号：US13243718
申请日：2011-09-23
申请人： Kap-Seok KANG , Jae-Woo PARK , Sang-Uk PARK , Yu-Kyung SIM , Keun-Sik LEE
发明人： Kap-Seok KANG , Jae-Woo PARK , Sang-Uk PARK , Yu-Kyung SIM , Keun-Sik LEE
IPC分类号： G03F1/50
CPC分类号： G03F1/54 , G03F1/50
摘要： A half tone mask having a multi semi-transmission part and a manufacturing method thereof that can pattern a plurality of layers using one mask, by having at least two or more semi-transmission parts with light transmission that are different from each other, are provided. The half tone mask having a multi semi-transmission part includes a transparent substrate, a light transmission part formed the transparent substrate to transmit irradiation light of a predetermined wavelength band, a light shielding part formed the transparent substrate to shield the irradiation light of the predetermined wavelength band, and at least two or more semi-transmission parts formed by depositing semi-transmission material on the transparent substrate to pass through the irradiation light of the predetermined wavelength band with each different light transmission.
摘要翻译：提供具有多重半透射部分的半色调掩模及其制造方法，其可以通过具有至少两个或更多个具有彼此不同的透光的半透射部分，使用一个掩模对多个层进行图案化。具有多重半透射部分的半色调掩模包括透明基板，形成透明基板以透射预定波长带的照射光的透光部分，形成透明基板的遮光部分，以屏蔽预定波长带的照射光以及通过在透明基板上沉积半透射材料而形成的至少两个或更多个半透射部分，以通过每种不同光透射的预定波长带的照射光。

8. 发明申请

US20120319112A1 THIN FILM TRANSISTOR, THIN FILM TRANSISTOR PANEL AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管，薄膜晶体管板及其制造方法
公开(公告)号：US20120319112A1
公开(公告)日：2012-12-20
申请号：US13223746
申请日：2011-09-01
申请人： Sung-Haeng CHO , Jae-Woo PARK , Do-Hyun KIM
发明人： Sung-Haeng CHO , Jae-Woo PARK , Do-Hyun KIM
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/78618
摘要： A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and a drain electrode and a source electrode on the oxide semiconductor layer and spaced apart from each other. The drain electrode includes a first drain sub-electrode on the oxide semiconductor layer, and a second drain sub-electrode on the first drain sub-electrode. The source electrode includes a first source sub-electrode on the oxide semiconductor layer, and a second source sub-electrode on the first source sub-electrode. The first drain sub-electrode and the first source sub-electrode include gallium zinc oxide (GaZnO), and the second source sub-electrode and the second drain sub-electrode include a metal atom.
摘要翻译：薄膜晶体管包括栅极电极，栅极绝缘层，栅极绝缘层上的氧化物半导体层，以及氧化物半导体层上的间隔开的漏电极和源电极。漏极包括氧化物半导体层上的第一漏极子电极和第一漏极子电极上的第二漏极子电极。源电极包括氧化物半导体层上的第一源子电极和第一源子电极上的第二源子电极。第一漏极子电极和第一源极电极包括镓锌氧化物（GaZnO），第二源极子电极和第二漏极子电极包括金属原子。

9. 发明申请

US20100023817A1 TEST SYSTEM AND METHOD 审中-公开
标题翻译：测试系统和方法
公开(公告)号：US20100023817A1
公开(公告)日：2010-01-28
申请号：US12499977
申请日：2009-07-09
申请人： Jae-Woo PARK , Jae-Yong JEONG
发明人： Jae-Woo PARK , Jae-Yong JEONG
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/08 , G11C16/04 , G11C2029/0401 , G11C2029/0405 , G11C2029/0409
摘要： A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.
摘要翻译：测试系统包括具有连接到数据写入路径和数据读出路径的数据I / O电路的存储器设备。在测试模式期间，数据I / O电路通过数据写入路径保留在I / O电路中接收的测试图形数据的副本作为测试图形数据作为输出测试数据存储在存储单元阵列中作为写入数据。测试系统还包括产生测试图案数据的测试设备，从存储设备接收输出测试数据，将输出测试数据与测试模式数据进行比较，并且基于比较生成错误检测信号。错误检测信号表示数据写入或读出路径中存在或不存在缺陷。

10. 发明申请

US20110192800A1 MAGNETIC-CORED DENDRIMER, THE METHOD FOR PREPARING THE SAME, AND THE CONTAMINANT TREATMENT METHOD USING THE SAME 审中-公开
标题翻译：磁性硬化剂，其制备方法和使用该方法的污染物处理方法
公开(公告)号：US20110192800A1
公开(公告)日：2011-08-11
申请号：US12856823
申请日：2010-08-16
申请人： Jae-Woo PARK , Jun-Won JANG , Han-Uk Lee
发明人： Jae-Woo PARK , Jun-Won JANG , Han-Uk Lee
IPC分类号： C02F1/42 , C07F7/10 , C07F7/18 , B82Y5/00
CPC分类号： B01J20/223 , B82Y40/00 , C01G49/02 , C01G49/04 , C01G49/06 , C01G49/08 , C02F1/285 , C02F1/288 , C02F1/488 , C02F1/66 , C02F2101/20 , C02F2303/16 , C02F2305/08 , C07B2200/11 , C07F7/1804 , H01B1/02 , H01B1/08 , H01B1/12
摘要： Provided is a magnetic-cored dendrimer represented by the following Chemical Formula (1): wherein A represents a metal nanoparticle; Z is a hydrophilic functional group or hydrophobic functional group; and m and n each represent an integer 1 or larger. More particularly, provided are a magnetic-cored dendrimer end-capped with hydrophilic or hydrophobic terminal groups, and a method for preparing the same. The magnetic-cored dendrimer may be used to adsorb and separate contaminants in a simple and effective manner.
摘要翻译：提供由以下化学式（1）表示的磁芯树枝状聚合物：其中A表示金属纳米颗粒; Z是亲水官能团或疏水官能团; m和n分别表示1以上的整数。更具体地说，提供端封有亲水或疏水性端基的磁芯树枝状聚合物及其制备方法。磁芯树枝状聚合物可用于以简单有效的方式吸附和分离污染物。

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