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    • 5. 发明申请
    • SYSTEMS AND METHODS FOR IMPROVED CHIP DEVICE PERFORMANCE
    • 改进芯片设备性能的系统和方法
    • US20120113615A1
    • 2012-05-10
    • US13250654
    • 2011-09-30
    • Jayesh NathYing Shen
    • Jayesh NathYing Shen
    • H05K7/00H05K3/10
    • H01P3/081H01L23/481H01L23/66H01L2223/6616H01L2223/6627H01L2223/6683H01L2924/0002Y10T29/49155H01L2924/00
    • Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.
    • 本文讨论了用于改善芯片器件性能的系统和方法。 用于集成电路的示例性芯片装置包括底部和与底部相对的顶部。 芯片器件包括片上器件互连和间隙区域。 片上器件互连被配置为提供底部的接地平面迹线与芯片器件顶部上的芯片器件路径之间的电连接。 芯片器件底部的间隙区域包括导电物质。 间隙区域的大小和形状有助于阻抗匹配。 芯片器件顶部上的芯片器件路径还可以包括至少一个调谐短截线。 至少一个调谐短截线的尺寸和形状也有助于阻抗匹配。