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1. 发明授权

US08001503B2 Method and system for automatically accessing internal signals or ports in a design hierarchy 有权
标题翻译：自动访问设计层级结构内部信号或端口的方法和系统
公开(公告)号：US08001503B2
公开(公告)日：2011-08-16
申请号：US11955689
申请日：2007-12-13
申请人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
发明人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.
摘要翻译：公开了一种采用分层路径数据库生成器来访问集成电路设计的设计层级中的内部信号或端口名称的方法。该方法包括将设计文件输入到分层路径数据库生成器中的步骤; 并且所述分级路径数据库生成器确定所述设计文件中的端口和信号，并且以逻辑层级顺序将所述端口和信号的名称存储在分层数据库中。该方法还包括提供测试用例以验证集成电路设计的定义方面的步骤; 解析测试用例以识别其中的所有信号和端口名称; 并且对于在测试用例中识别的每个信号和端口名称，将所述每个名称输入到分层路径数据库生成器中，并从该生成器获得与所述每个信号和端口名称相关联的分层路径。

2. 发明申请

US20090158225A1 METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY 有权
标题翻译：用于在设计层次上自动访问内部信号或端口的方法和系统
公开(公告)号：US20090158225A1
公开(公告)日：2009-06-18
申请号：US11955689
申请日：2007-12-13
申请人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
发明人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.
摘要翻译：公开了一种采用分层路径数据库生成器来访问集成电路设计的设计层级中的内部信号或端口名称的方法。该方法包括将设计文件输入到分层路径数据库生成器中的步骤; 并且所述分级路径数据库生成器确定所述设计文件中的端口和信号，并且以逻辑层级顺序将所述端口和信号的名称存储在分层数据库中。该方法还包括提供测试用例以验证集成电路设计的定义方面的步骤; 解析测试用例以识别其中的所有信号和端口名称; 并且对于在测试用例中识别的每个信号和端口名称，将所述每个名称输入到分层路径数据库生成器中，并从该生成器获得与所述每个信号和端口名称相关联的分层路径。

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