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1. 发明授权

US07602974B2 Universal fixed-pixel-size ISP scheme 失效
标题翻译：通用固定像素尺寸ISP方案
公开(公告)号：US07602974B2
公开(公告)日：2009-10-13
申请号：US11255373
申请日：2005-10-21
申请人： Jau-Wen Ren
发明人： Jau-Wen Ren
IPC分类号： G06K9/36 , G06K9/46 , H04N1/413 , H04N1/41
CPC分类号： H04N1/40
摘要： An Image Signal Processing unit (ISP) has at least one fixed-size line buffer which is smaller than the width of the image buffer. To handle the image data, the image buffer is divided into regions which are sequentially loaded into the at least one fixed-size line buffer of the ISP for processing. Since functions of the ISP operate with neighboring pixels of the target pixel, margins of the regions need to be transmitted as well. After processing by the ISP, the data is encoded which includes a DCT, Quantization, and VLC. The result is then stored in segments in a buffer storage. VLC also inserts a Restart Marker which is used as a pointer to stitch together all the segments thus producing a new and seamless image.
摘要翻译：图像信号处理单元（ISP）具有至少一个小于图像缓冲器的宽度的固定大小的行缓冲器。为了处理图像数据，图像缓冲器被划分为顺序地加载到ISP的至少一个固定大小的行缓冲器中以进行处理的区域。由于ISP的功能与目标像素的相邻像素一起工作，所以区域的边缘也需要传输。在ISP处理之后，数据被编码，包括DCT，量化和VLC。然后将结果存储在缓冲存储器中的段中。 VLC还插入一个重新启动标记，该标记用作指针，以将所有段拼接在一起，从而产生新的无缝图像。

2. 发明授权

US07984211B2 Self-synchronizing hardware/software interface for multimedia SOC design 失效
标题翻译：用于多媒体SOC设计的自同步硬件/软件界面
公开(公告)号：US07984211B2
公开(公告)日：2011-07-19
申请号：US12575446
申请日：2009-10-07
申请人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Shankar Durvasula , Jau-Wen Ren
发明人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Shankar Durvasula , Jau-Wen Ren
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4234 , G06F2213/0038 , H04N21/443
摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.
摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。硬件检查消息队列的内容，并开始对传入的数据进行解码。硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。当达到End标签时，硬件会向CPU提供中断信号给CPU。可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

3. 发明申请

US20070091379A1 Universal fixed-pixel-size ISP scheme 审中-公开
标题翻译：通用固定像素尺寸ISP方案
公开(公告)号：US20070091379A1
公开(公告)日：2007-04-26
申请号：US11255374
申请日：2005-10-21
申请人： Jau-Wen Ren
发明人： Jau-Wen Ren
IPC分类号： H04N1/413
CPC分类号： H04N1/40
摘要： An Image Signal Processing unit (ISP) has a fixed-size line buffer which is smaller than the width of the image buffer. To handle the image data, the image buffer is divided into regions which are sequentially loaded into the fixed-size line buffer of the ISP for processing. Since functions of the ISP operate with neighboring pixels of the target pixel, margins of the regions need to be transmitted as well.
摘要翻译：图像信号处理单元（ISP）具有小于图像缓冲器的宽度的固定大小的行缓冲器。为了处理图像数据，将图像缓冲器划分为依次加载到ISP的固定大小的行缓冲器中进行处理的区域。由于ISP的功能与目标像素的相邻像素一起工作，所以区域的边缘也需要传输。

4. 发明授权

US07974480B2 Universal fixed-pixel-size ISP scheme 失效
标题翻译：通用固定像素尺寸ISP方案
公开(公告)号：US07974480B2
公开(公告)日：2011-07-05
申请号：US12551406
申请日：2009-08-31
申请人： Jau-Wen Ren
发明人： Jau-Wen Ren
IPC分类号： G06K9/36 , G06K9/46 , H04N1/413 , H04N1/41
CPC分类号： H04N1/40
摘要： An Image Signal Processing unit (ISP) has at least one fixed-size line buffer which is smaller than the width of the image buffer. To handle the image data, the image buffer is divided into regions which are sequentially loaded into the at least one fixed-size line buffer of the ISP for processing. Since functions of the ISP operate with neighboring pixels of the target pixel, margins of the regions need to be transmitted as well. After processing by the ISP, the data is encoded which includes a DCT, Quantization, and VLC. The result is then stored in segments in a buffer storage. VLC also inserts a Restart Marker which is used as a pointer to stitch together all the segments thus producing a new and seamless image.
摘要翻译：图像信号处理单元（ISP）具有至少一个小于图像缓冲器的宽度的固定大小的行缓冲器。为了处理图像数据，图像缓冲器被划分为顺序地加载到ISP的至少一个固定大小的行缓冲器中以进行处理的区域。由于ISP的功能与目标像素的相邻像素一起工作，所以区域的边缘也需要传输。在ISP处理之后，数据被编码，包括DCT，量化和VLC。然后将结果存储在缓冲存储器中的段中。 VLC还插入一个重新启动标记，该标记用作指针，以将所有段拼接在一起，从而产生新的无缝图像。

5. 发明申请

US20070091378A1 Universal fixed-pixel-size ISP scheme 失效
标题翻译：通用固定像素尺寸ISP方案
公开(公告)号：US20070091378A1
公开(公告)日：2007-04-26
申请号：US11255373
申请日：2005-10-21
申请人： Jau-Wen Ren
发明人： Jau-Wen Ren
IPC分类号： H04N1/413
CPC分类号： H04N1/40
摘要： An Image Signal Processing unit (ISP) has at least one fixed-size line buffer which is smaller than the width of the image buffer. To handle the image data, the image buffer is divided into regions which are sequentially loaded into the at least one fixed-size line buffer of the ISP for processing. Since functions of the ISP operate with neighboring pixels of the target pixel, margins of the regions need to be transmitted as well. After processing by the ISP, the data is encoded which includes a DCT, Quantization, and VLC. The result is then stored in segments in a buffer storage. VLC also inserts a Restart Marker which is used as a pointer to stitch together all the segments thus producing a new and seamless image.
摘要翻译：图像信号处理单元（ISP）具有至少一个小于图像缓冲器的宽度的固定大小的行缓冲器。为了处理图像数据，图像缓冲器被划分为顺序地加载到ISP的至少一个固定大小的行缓冲器中以进行处理的区域。由于ISP的功能与目标像素的相邻像素一起工作，所以区域的边缘也需要传输。在ISP处理之后，数据被编码，包括DCT，量化和VLC。然后将结果存储在缓冲存储器中的段中。 VLC还插入一个重新启动标记，该标记用作指针，以将所有段拼接在一起，从而产生新的无缝图像。

6. 发明授权

US07707334B2 Self-synchronizing hardware/software interface for multimedia SOC design 失效
标题翻译：用于多媒体SOC设计的自同步硬件/软件界面
公开(公告)号：US07707334B2
公开(公告)日：2010-04-27
申请号：US11282531
申请日：2005-11-18
申请人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Shankar Durvasula , Jau-Wen Ren
发明人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Shankar Durvasula , Jau-Wen Ren
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4234 , G06F2213/0038 , H04N21/443
摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.
摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。硬件检查消息队列的内容，并开始对传入的数据进行解码。硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。当达到End标签时，硬件会向CPU提供中断信号给CPU。可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

7. 发明申请

US20070130394A1 Self-synchronizing hardware/software interface for multimedia SOC design 失效
标题翻译：用于多媒体SOC设计的自同步硬件/软件界面
公开(公告)号：US20070130394A1
公开(公告)日：2007-06-07
申请号：US11282531
申请日：2005-11-18
申请人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Durvasula , Jau-Wen Ren
发明人： Lincheng Wang , Ching-Han Tsai , Cheng-Lun Chang , Uma Durvasula , Jau-Wen Ren
IPC分类号： G06F5/00
CPC分类号： G06F13/4234 , G06F2213/0038 , H04N21/443
摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.
摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。硬件检查消息队列的内容，并开始对传入的数据进行解码。硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。当达到End标签时，硬件会向CPU提供中断信号给CPU。可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

8. 发明授权

US06370067B1 Automatic configuration of delay parameters in a dynamic memory controller 失效
标题翻译：在动态存储控制器中自动配置延迟参数
公开(公告)号：US06370067B1
公开(公告)日：2002-04-09
申请号：US09772111
申请日：2001-01-25
申请人： Ka-pui Ko , Isaac H. Wong , Keith V. Ngo , Jau-Wen Ren , Jiinyuan Lee
发明人： Ka-pui Ko , Isaac H. Wong , Keith V. Ngo , Jau-Wen Ren , Jiinyuan Lee
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/16 , G11C29/38 , G11C29/50
摘要： A memory controller configured according to a delay pair for communicating with a memory device automatically selects optimal delay pairs by testing whether successful communication exists at various values for the delay pairs. The resulting set of delay pairs allowing successful communication are divided into a boundary set and non-boundary set. An optimal delay pair from the non-boundary set is chosen according to its relationship to delay pairs in the boundary set.
摘要翻译：根据用于与存储器件通信的延迟对配置的存储器控制器通过测试延迟对的各种值是否存在成功通信来自动选择最佳延迟对。所得到的允许成功通信的延迟对的组被划分为边界集和非边界集合。根据与边界集中的延迟对的关系，选择来自非边界集合的最佳延迟对。

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