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1. 发明授权

US08418093B2 Method and system for design simplification through implication-based analysis 失效
标题翻译：通过暗示分析进行设计简化的方法和系统
公开(公告)号：US08418093B2
公开(公告)日：2013-04-09
申请号：US12467097
申请日：2009-05-15
申请人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Robert L. Kanzelman
发明人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Robert L. Kanzelman
IPC分类号： G06F9/45
CPC分类号： G06F17/505
摘要： Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplified circuit design is a suitable replacement for the original circuit design.
摘要翻译：提供了方法和系统，用于通过合并可能不相等但可被证明能够保持目标可靠性的原始电路设计的门来将原始电路设计减少为简化的电路设计。复合网表由简化网表和原网表创建。复合网表包括许多目标，这些目标意味着简化网表中存在目标，而在原始网表中存在相应的目标。这些含义经过验证，然后得到验证，以确保简化的电路设计是原始电路设计的合适替代品。

2. 发明授权

US08589327B2 Efficiently determining boolean satisfiability with lazy constraints 失效
标题翻译：有效地确定具有延迟约束的布尔可满足性
公开(公告)号：US08589327B2
公开(公告)日：2013-11-19
申请号：US13092262
申请日：2011-04-22
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译：提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。确定SAT问题是否满足约束列表中的约束。响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。

3. 发明授权

US08418106B2 Techniques for employing retiming and transient simplification on netlists that include memory arrays 失效
标题翻译：对包含存储器阵列的网表进行重新定时和瞬态简化的技术
公开(公告)号：US08418106B2
公开(公告)日：2013-04-09
申请号：US12872490
申请日：2010-08-31
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译：用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。然后基于减少信息来修改网表。

4. 发明申请

US20120290992A1 LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES 失效
标题翻译：使用包含符号值的模拟结果的逻辑电路网络列表减少和模型简化
公开(公告)号：US20120290992A1
公开(公告)日：2012-11-15
申请号：US13104573
申请日：2011-05-10
申请人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
发明人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
摘要翻译：用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。

5. 发明授权

US08146034B2 Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. 有权
标题翻译：有效的冗余识别，冗余删除和在包括内存数组的设计中的顺序等价检查。
公开(公告)号：US08146034B2
公开(公告)日：2012-03-27
申请号：US12771677
申请日：2010-04-30
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.
摘要翻译：提供了一种机制，用于有效的冗余识别，冗余删除和与包括存储器阵列的设计的顺序等同性检查。该机制包括阵列合并组件，以最佳地合并阵列输出，以便如果地址超出边界或端口未被断言，阵列输出将转换为随机输出。该机制还包括用于确定启用的阵列输出的等效性的组件，而不是直接对阵列输出进行创建并创建启用的阵列输出。该机制还包括排除潜在冗余阵列单元参与顺序冗余移除确定的组件。该组件首先检查相应阵列的兼容性，然后对应的读端口启用和地址，然后对应的初始值，最后检查对相应列的写入是否产生兼容的值集合。

6. 发明授权

US08589837B1 Constructing inductive counterexamples in a multi-algorithm verification framework 失效
标题翻译：在多算法验证框架中构建归纳反例
公开(公告)号：US08589837B1
公开(公告)日：2013-11-19
申请号：US13455839
申请日：2012-04-25
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504
摘要： A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process. Adding the projected state information as an invariant ensures that any resulting induction counterexamples can be mapped to valid induction counterexamples on the original netlist before undergoing the simplification.
摘要翻译：计算机实现的方法简化网表，使用归纳验证简化的网表，并通过多算法验证框架内的归纳跟踪提升重新生成归纳反例。该方法包括：处理器导出可用于简化网表的第一不可达状态信息; 利用第一不可达状态信息来执行网表的简化; 确定在网表的原始版本上是否可以感应地证明第一不可达状态信息; 并且响应于在原始网表上不被感应地证明的第一不可达状态信息：将第一不可达状态信息投射到最小子集; 并且将预测的不可达状态信息添加为不变量以进一步约束儿童归纳过程。将投影状态信息添加为不变量确保在进行简化之前，任何导致的归因反例可以映射到原始网表上的有效归纳反例。

7. 发明授权

US08307313B2 Minimizing memory array representations for enhanced synthesis and verification 有权
标题翻译：最小化存储器阵列表示，以增强综合和验证
公开(公告)号：US08307313B2
公开(公告)日：2012-11-06
申请号：US12775607
申请日：2010-05-07
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50 , G06F9/455 , G06F15/16
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.
摘要翻译：在用于最小化存储器阵列表示以用于增强的合成和验证的设计环境中提供机制。设计环境包括使用断开的引脚信息压缩阵列宽度的一种机制。设计环境包括使用无关心计算简化阵列端口使能条件的另一种机制。设计环境包括通过分析可读地址的限制来减少地址引脚从阵列的另一机制。

8. 发明申请

US20120054701A1 Optimal Correlated Array Abstraction 有权
标题翻译：最优相关数组抽象
公开(公告)号：US20120054701A1
公开(公告)日：2012-03-01
申请号：US12871962
申请日：2010-08-31
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504
摘要： Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist. In addition, the mechanisms utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.
摘要翻译：提供了用于改进用于验证或综合集成电路设计的网表的抽象的机制。这些机制接收到与集成电路设计的原始网表相对应的抽象网表。这些机制确定已经存在于抽象网表中的元素，并通过扩展抽象网表来改进抽象网表，以包括与抽象网表中已经存在的元素相关联的附加元素，从而生成精简抽象网表。另外，这些机制利用精简的抽象网表来执行集成电路设计的验证或合成中的至少一个。

9. 发明授权

US09280626B2 Efficiently determining Boolean satisfiability with lazy constraints 有权
标题翻译：通过延迟约束有效地确定布尔可满足性
公开(公告)号：US09280626B2
公开(公告)日：2016-03-08
申请号：US13458252
申请日：2012-04-27
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F9/44 , G06N7/02 , G06N7/06 , G06F17/50 , G06F17/11
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译：提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。确定SAT问题是否满足约束列表中的约束。响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。

10. 发明授权

US08578311B1 Method and system for optimal diameter bounding of designs with complex feed-forward components 失效
标题翻译：具有复杂前馈组件的设计的最佳直径界限的方法和系统
公开(公告)号：US08578311B1
公开(公告)日：2013-11-05
申请号：US13467425
申请日：2012-05-09
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC.
摘要翻译：计算机实现的方法包括处理器，其在网表内识别至少一个强连接组件（SCC），其具有从具有与SCC不同的传播延迟的再聚合扇区输入的至少两个输入路径的重新接收扇区输入。该方法然后计算包括至少一个SCC的网表的添加剂直径，其中添加剂直径包括基于至少两个输入路径到SCC的传播延迟差和多个复合前馈确定的扇形添加剂直径在至少一个输入路径内的组件。响应于提供一个功能的SCC的再混合扇区输入，该方法利用从通向SCC的每个再聚合扇区输入上的一个或多个传播延迟差导出的最小公倍数（LCM）来计算SCC的乘法直径。

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