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1. 发明授权

US07620776B2 Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks 有权
标题翻译：用于预测修改的存储器块的位置的高速缓存一致性协议状态的方法，装置和计算机程序产品
公开(公告)号：US07620776B2
公开(公告)日：2009-11-17
申请号：US11954742
申请日：2007-12-12
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/76
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache coherency protocol state is defined that predicts whether a memory access request to read or write data in a cache line can be satisfied within a local node. When a cache line is in the modified invalid state, the only valid copies of the data are predicted to be located in the local node. When a cache line is in the invalid state and not in the modified invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory access requests to read exclusive or write data in a cache line that is not currently in the modified invalid state are broadcast first to all nodes. Memory access requests to read exclusive or write data in a cache line that is currently in the modified invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory access requests within the local node, the memory access requests are broadcast to the remote nodes.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于减少不必要地广播的远程请求的数量，以减少从本地节点访问数据的等待时间并减少SMP计算机系统中的全局流量。定义了修改的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在高速缓存行中读取或写入数据的存储器访问请求。当缓存行处于修改的无效状态时，数据的唯一有效副本被预测位于本地节点中。当高速缓存行处于无效状态而不处于修改的无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到所有节点。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器访问请求，存储器访问请求广播到远程节点。

2. 发明授权

US07747825B2 Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks 有权
标题翻译：用于预测共享存储器块的位置的高速缓存一致性协议状态的方法，装置和计算机程序产品
公开(公告)号：US07747825B2
公开(公告)日：2010-06-29
申请号：US12107350
申请日：2008-04-22
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is defined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory read requests to read data in a cache line that is not currently in the shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.
摘要翻译：公开了用于减少不必要地广播的本地请求的数量以减少从SMP计算机系统中的远程节点访问数据的等待时间的方法，装置和计算机程序产品。定义共享的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在共享高速缓存行中读取数据的存储器读取请求。当高速缓存行处于共享无效状态时，预测数据的有效副本位于本地节点中。当高速缓存行处于无效状态而不处于共享无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于共享无效状态的缓存行中读取数据的内存读取请求首先被广播到远程节点。在当前处于共享无效状态的高速缓存行中读取数据的存储器读取请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器读取请求，存储器读取请求被广播到远程节点。

3. 发明申请

US20080215819A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR A CACHE COHERENCY PROTOCOL STATE THAT PREDICTS LOCATIONS OF SHARED MEMORY BLOCKS 有权
标题翻译：用于预测共享存储块位置的高速缓存协议状态的方法，设备和计算机程序产品
公开(公告)号：US20080215819A1
公开(公告)日：2008-09-04
申请号：US12107350
申请日：2008-04-22
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is defined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory read requests to read data in a cache line that is not currently in the shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.
摘要翻译：公开了用于减少不必要地广播的本地请求的数量以减少从SMP计算机系统中的远程节点访问数据的等待时间的方法，装置和计算机程序产品。定义共享的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在共享高速缓存行中读取数据的存储器读取请求。当高速缓存行处于共享无效状态时，预测数据的有效副本位于本地节点中。当高速缓存行处于无效状态而不处于共享无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于共享无效状态的缓存行中读取数据的内存读取请求首先被广播到远程节点。在当前处于共享无效状态的高速缓存行中读取数据的存储器读取请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器读取请求，存储器读取请求被广播到远程节点。

4. 发明授权

US07395376B2 Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks 有权
标题翻译：用于预测共享存储器块的位置的高速缓存一致性协议状态的方法，装置和计算机程序产品
公开(公告)号：US07395376B2
公开(公告)日：2008-07-01
申请号：US11184315
申请日：2005-07-19
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is declined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes. Memory read requests to read data in a cache line that is not currently in tile shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.
摘要翻译：公开了用于减少不必要地广播的本地请求的数量以减少从SMP计算机系统中的远程节点访问数据的等待时间的方法，装置和计算机程序产品。共享的无效高速缓存一致性协议状态被拒绝，该状态预测在本地节点内是否可以满足在共享高速缓存行中读取数据的存储器读取请求。当高速缓存行处于共享无效状态时，预测数据的有效副本位于本地节点中。当高速缓存行处于无效状态而不处于共享无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于瓦片共享无效状态的缓存行中读取数据的内存读取请求首先被广播到远程节点。在当前处于共享无效状态的高速缓存行中读取数据的存储器读取请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器读取请求，存储器读取请求被广播到远程节点。

5. 发明授权

US07360032B2 Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks 失效
标题翻译：用于预测修改的存储器块的位置的高速缓存一致性协议状态的方法，装置和计算机程序产品
公开(公告)号：US07360032B2
公开(公告)日：2008-04-15
申请号：US11184314
申请日：2005-07-19
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache coherency protocol state is defined that predicts whether a memory access request to read or write data in a cache line can be satisfied within a local node. When a cache line is in the modified invalid state, the only valid copies of the data are predicted to be located in the local node. When a cache line is in the invalid state and not in the modified invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory access requests to read exclusive or write data in a cache line that is not currently in the modified invalid state are broadcast first to all nodes. Memory access requests to read exclusive or write data in a cache line that is currently in the modified invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory access requests within the local node, the memory access requests are broadcast to the remote nodes.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于减少不必要地广播的远程请求的数量，以减少从本地节点访问数据的等待时间并减少SMP计算机系统中的全局流量。定义了修改的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在高速缓存行中读取或写入数据的存储器访问请求。当缓存行处于修改的无效状态时，数据的唯一有效副本被预测位于本地节点中。当高速缓存行处于无效状态而不处于修改的无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到所有节点。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器访问请求，存储器访问请求广播到远程节点。

6. 发明授权

US06960941B2 Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits 失效
标题翻译：锁存电路能够确保动态逻辑电路中信号的无竞争分级
公开(公告)号：US06960941B2
公开(公告)日：2005-11-01
申请号：US10803588
申请日：2004-03-18
申请人： Jason Frederick Cantin , Michael Ju Hyeok Lee
发明人： Jason Frederick Cantin , Michael Ju Hyeok Lee
IPC分类号： H03F3/45 , H03K3/037 , H03K3/356 , H03K19/096
CPC分类号： H03K3/0375
摘要： A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.
摘要翻译：公开了一种能够确保动态逻辑电路中的信号的无竞争阶段的锁存电路。锁存电路包括四个单独的逻辑门。第一和第二逻辑门的第一输入分别连接到动态逻辑电路的第一和第二预充电内部节点。第一和第二栅极的第二输入分别连接到动态逻辑电路的第一和第二差分输出端。第三和第四门的第一输入分别连接到第一和第二逻辑门的输出端。第四栅极的第二输入端连接到第三逻辑门的输出端以提供锁存电路的第一输出。类似地，第三逻辑门的第二输入连接到第四逻辑门的输出，以提供锁存电路的第二输出。

7. 发明授权

US08615636B2 Multiple-class priority-based replacement policy for cache memory 失效
标题翻译：用于缓存的多类优先级替换策略
公开(公告)号：US08615636B2
公开(公告)日：2013-12-24
申请号：US13039755
申请日：2011-03-03
申请人： Jason Frederick Cantin , Prasenjit Chakraborty
发明人： Jason Frederick Cantin , Prasenjit Chakraborty
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： This invention is a method and system for replacing an entry in a cache memory (replacement policy). The cache is divided into a high-priority class and a low-priority class. Upon a request for information such as data, an instruction, or an address translation, the processor searches the cache. If there is a cache miss, the processor locates the information elsewhere, typically in memory. The found information replaces an existing entry in the cache. The entry selected for replacement (eviction) is chosen from within the low-priority class using a FIFO algorithm. Upon a cache hit, the processor performs a read, write, or execute using or upon the information. If the performed instruction was a “write”, the information is placed into the high-priority class. If the high-priority class is full, an entry within the high-priority class is selected for removal based on a FIFO algorithm, and re-classified into the low-priority class.
摘要翻译：本发明是用于替换高速缓冲存储器（替换策略）中的条目的方法和系统。高速缓存分为高优先级类和低优先级类。当请求诸如数据，指令或地址转换之类的信息时，处理器搜索高速缓存。如果存在高速缓存未命中，则处理器将信息定位在其他地方，通常在内存中。找到的信息替换缓存中的现有条目。使用FIFO算法从低优先级类别中选择用于替换（逐出）的条目。在缓存命中时，处理器使用或在信息上执行读取，写入或执行。如果执行的指令是“写入”，则将信息放入高优先级类。如果高优先级级别已满，则根据FIFO算法选择高优先级类别中的条目进行删除，并将其重新分类为低优先级类。

8. 发明申请

US20120226871A1 MULTIPLE-CLASS PRIORITY-BASED REPLACEMENT POLICY FOR CACHE MEMORY 失效
标题翻译：用于高速缓存存储器的多级优先级更换策略
公开(公告)号：US20120226871A1
公开(公告)日：2012-09-06
申请号：US13039755
申请日：2011-03-03
申请人： Jason Frederick Cantin , Prasenjit Chakraborty
发明人： Jason Frederick Cantin , Prasenjit Chakraborty
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/123
摘要： This invention is a method and system for replacing an entry in a cache memory (replacement policy). The cache is divided into a high-priority class and a low-priority class. Upon a request for information such as data, an instruction, or an address translation, the processor searches the cache. If there is a cache miss, the processor locates the information elsewhere, typically in memory. The found information replaces an existing entry in the cache. The entry selected for replacement (eviction) is chosen from within the low-priority class using a FIFO algorithm. Upon a cache hit, the processor performs a read, write, or execute using or upon the information. If the performed instruction was a “write”, the information is placed into the high-priority class. If the high-priority class is full, an entry within the high-priority class is selected for removal based on a FIFO algorithm, and re-classified into the low-priority class.
摘要翻译：本发明是用于替换高速缓冲存储器（替换策略）中的条目的方法和系统。高速缓存分为高优先级类和低优先级类。当请求诸如数据，指令或地址转换之类的信息时，处理器搜索高速缓存。如果存在高速缓存未命中，则处理器将信息定位在其他地方，通常在内存中。找到的信息替换缓存中的现有条目。使用FIFO算法从低优先级类别中选择用于替换（逐出）的条目。在缓存命中时，处理器使用或在信息上执行读取，写入或执行。如果执行的指令是“写入”，则将信息放入高优先级类。如果高优先级级别已满，则根据FIFO算法选择高优先级类别中的条目进行删除，并将其重新分类为低优先级类。

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