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1. 发明授权

US08790991B2 Method and structure for shallow trench isolation to mitigate active shorts 有权
标题翻译：浅沟槽隔离的方法和结构，以减轻主动短裤
公开(公告)号：US08790991B2
公开(公告)日：2014-07-29
申请号：US13011546
申请日：2011-01-21
申请人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76 , H01L21/762 , H01L21/02 , H01L21/8234 , H01L29/06
CPC分类号： H01L21/76224 , H01L21/02107 , H01L21/823481 , H01L21/823878 , H01L29/0649 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.
摘要翻译：提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料氧化物。

2. 发明授权

US08232179B2 Method to improve wet etch budget in FEOL integration 有权
标题翻译：在FEOL集成中改善湿法蚀刻预算的方法
公开(公告)号：US08232179B2
公开(公告)日：2012-07-31
申请号：US12571483
申请日：2009-10-01
申请人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

3. 发明授权

US08679941B2 Method to improve wet etch budget in FEOL integration 失效
标题翻译：在FEOL集成中改善湿法蚀刻预算的方法
公开(公告)号：US08679941B2
公开(公告)日：2014-03-25
申请号：US13422138
申请日：2012-03-16
申请人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

4. 发明申请

US20120187523A1 METHOD AND STRUCTURE FOR SHALLOW TRENCH ISOLATION TO MITIGATE ACTIVE SHORTS 有权
标题翻译：用于缓解热量分解以缓解主动短裤的方法和结构
公开(公告)号：US20120187523A1
公开(公告)日：2012-07-26
申请号：US13011546
申请日：2011-01-21
申请人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76224 , H01L21/02107 , H01L21/823481 , H01L21/823878 , H01L29/0649 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.
摘要翻译：提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料氧化物。

5. 发明申请

US20120178236A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
标题翻译：提高生产费用总额的方法
公开(公告)号：US20120178236A1
公开(公告)日：2012-07-12
申请号：US13422138
申请日：2012-03-16
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

6. 发明申请

US20110081765A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
标题翻译：提高生产费用总额的方法
公开(公告)号：US20110081765A1
公开(公告)日：2011-04-07
申请号：US12571483
申请日：2009-10-01
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

7. 发明申请

US20130015512A1 LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效
公开(公告)号：US20130015512A1
公开(公告)日：2013-01-17
申请号：US13605260
申请日：2012-09-06
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

8. 发明申请

US20130015509A1 LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效
标题翻译： ETSOI的低电阻源和漏电延伸
公开(公告)号：US20130015509A1
公开(公告)日：2013-01-17
申请号：US13183666
申请日：2011-07-15
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译：在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

9. 发明授权

US08486778B2 Low resistance source and drain extensions for ETSOI 失效
公开(公告)号：US08486778B2
公开(公告)日：2013-07-16
申请号：US13183666
申请日：2011-07-15
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

10. 发明授权

US08614486B2 Low resistance source and drain extensions for ETSOI 失效
标题翻译：用于ETSOI的低电阻源和漏极扩展
公开(公告)号：US08614486B2
公开(公告)日：2013-12-24
申请号：US13605260
申请日：2012-09-06
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译：在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

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