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1. 发明申请

US20070228435A1 Semiconductor device and fabrication thereof 审中-公开
标题翻译：半导体器件及其制造
公开(公告)号：US20070228435A1
公开(公告)日：2007-10-04
申请号：US11476266
申请日：2006-06-28
申请人： Jar-Ming Ho , Shian-Jyh Lin , Chin-Tien Yang , Chien-Li Cheng
发明人： Jar-Ming Ho , Shian-Jyh Lin , Chin-Tien Yang , Chien-Li Cheng
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A method for forming a semiconductor device is disclosed, in which a substrate comprising a recessed gate is provided, and a protrusion of the recessed gate protrudes a surface of the substrate. A spacer is formed on a sidewall of the protrusion of the recessed gate. A conductive structure is formed overlying the recessed gate, wherein the conductive structure is narrower than the recessed gate to expose a portion of the recessed gate. An etching process is utilized to recess a exposed portion of the recessed gate, and form a recess portion between the recessed gate and the spacer. A conductive line spacer is formed on a sidewall of the conductive line structure, wherein the conductive line spacer fills the recessed portion.
摘要翻译：公开了一种用于形成半导体器件的方法，其中提供包括凹入栅极的衬底，并且凹入栅极的突起突出于衬底的表面。间隔件形成在凹入门的突起的侧壁上。导电结构形成在凹入栅极上，其中导电结构比凹入栅极窄，以暴露凹入栅极的一部分。利用蚀刻工艺来凹入凹入栅极的暴露部分，并在凹入栅极和间隔物之间形成凹陷部分。在导线结构的侧壁上形成导线间隔物，其中导线间隔物填充凹陷部分。

2. 发明授权

US07510930B2 Method for fabricating recessed gate MOS transistor device 有权
标题翻译：凹陷栅极MOS晶体管器件的制造方法
公开(公告)号：US07510930B2
公开(公告)日：2009-03-31
申请号：US11685756
申请日：2007-03-13
申请人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
发明人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L21/26586 , H01L21/28061 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66545
摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

3. 发明申请

US20090008692A1 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090008692A1
公开(公告)日：2009-01-08
申请号：US11966891
申请日：2007-12-28
申请人： Shian-Jyh Lin , Yu-Pi Lee , Ming-Yuan Huang , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
发明人： Shian-Jyh Lin , Yu-Pi Lee , Ming-Yuan Huang , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10894
摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.
摘要翻译：半导体器件包括半导体衬底。半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

4. 发明申请

US20080318388A1 METHOD FOR FABRICATING MOS TRANSISTOR WITH RECESS CHANNEL 审中-公开
标题翻译：用于制作带有通道的MOS晶体管的方法
公开(公告)号：US20080318388A1
公开(公告)日：2008-12-25
申请号：US11955405
申请日：2007-12-13
申请人： Shian-Jyh Lin , Yu-Pi Lee , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
发明人： Shian-Jyh Lin , Yu-Pi Lee , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
IPC分类号： H01L21/20
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7854
摘要： A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of the trench top oxide; forming a second spacer on the first spacer; defining a plurality of active areas, wherein each of the active areas is parallel with each other and comprises at least two of the trench capacitors; forming an isolation area between each of the active area; etching the substrate of the active area by using the second spacer as a mask to form a trench in the active area; removing the second spacer to expose a portion of the substrate, and etching the exposed substrate to enlarge the trench; and forming a gate structure in the trench.
摘要翻译：一种用于制造具有凹槽通道的MOS晶体管的方法，包括：在其中为衬底提供多个沟槽电容器，其中沟槽顶部氧化物位于每个沟槽电容器的顶部并且远离衬底表面延伸; 在所述沟槽顶部氧化物的侧壁上形成第一间隔物; 在所述第一间隔物上形成第二间隔物; 限定多个有效区域，其中每个有源区域彼此平行并且包括至少两个沟槽电容器; 在每个所述活动区域之间形成隔离区域; 通过使用第二间隔件作为掩模蚀刻有源区的衬底，以在有源区中形成沟槽; 去除所述第二间隔物以暴露所述衬底的一部分，并蚀刻所述暴露的衬底以扩大所述沟槽; 并在沟槽中形成栅极结构。

5. 发明申请

US20070264772A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE 有权
标题翻译：用于制造接收栅极MOS晶体管器件的方法
公开(公告)号：US20070264772A1
公开(公告)日：2007-11-15
申请号：US11685756
申请日：2007-03-13
申请人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
发明人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L21/26586 , H01L21/28061 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66545
摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

6. 发明授权

US07622381B2 Semiconductor structure and the forming method thereof 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US07622381B2
公开(公告)日：2009-11-24
申请号：US11829371
申请日：2007-07-27
申请人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
发明人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/76834 , H01L27/10888 , H01L27/10894
摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.
摘要翻译：本发明提供一种半导体结构及其形成方法。该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。

7. 发明申请

US20080217779A1 SEMICONDUCTOR STRUCTURE AND THE FORMING METHOD THEREOF 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20080217779A1
公开(公告)日：2008-09-11
申请号：US11829371
申请日：2007-07-27
申请人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
发明人： Jar-Ming Ho , Shian-Jyh Lin , Ming-Yuan Huang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76834 , H01L27/10888 , H01L27/10894
摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.
摘要翻译：本发明提供一种半导体结构及其形成方法。该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。

8. 发明授权

US07955927B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07955927B2
公开(公告)日：2011-06-07
申请号：US11966891
申请日：2007-12-28
申请人： Shian-Jyh Lin , Yu-Pi Lee , Ming-Yuan Huang , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
发明人： Shian-Jyh Lin , Yu-Pi Lee , Ming-Yuan Huang , Jar-Ming Ho , Shun-Fu Chen , Tse-Chuan Kuo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10894
摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.
摘要翻译：半导体器件包括半导体衬底。半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

9. 发明申请

US20070155179A1 METHOD TO DEFINE A PATTERN HAVING SHRUNK CRITICAL DIMENSION 审中-公开
标题翻译：定义具有SHRUNK关键尺寸的图案的方法
公开(公告)号：US20070155179A1
公开(公告)日：2007-07-05
申请号：US11456207
申请日：2006-07-09
申请人： Jar-Ming Ho , Shian-Jyh Lin , Yu-Pi Lee
发明人： Jar-Ming Ho , Shian-Jyh Lin , Yu-Pi Lee
IPC分类号： H01L21/311 , H01L21/76 , H01L21/3205 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/1087
摘要： The present invention provides a method for fabricating a trench opening in a semiconductor substrate. The patterned amorphous silicon layer is completely oxidized to form a silicon oxide mask having openings with shrunk critical dimensions. The silicon oxide mask is used as an etching hard mask in the subsequent trench etching process. The present invention is not only suited for the fabrication of trench-capacitor DRAM devices, but also suited for the semiconductor contact/via processes.
摘要翻译：本发明提供一种在半导体衬底中制造沟槽开口的方法。图案化的非晶硅层被完全氧化以形成具有收缩临界尺寸的开口的氧化硅掩模。在随后的沟槽蚀刻工艺中，氧化硅掩模用作蚀刻硬掩模。本发明不仅适用于制造沟槽电容器DRAM器件，而且也适用于半导体接触/通孔工艺。

10. 发明申请

US20120267727A1 METHOD FOR FORMING SELF-ALIGNED CONTACT 有权
标题翻译：形成自对准接触的方法
公开(公告)号：US20120267727A1
公开(公告)日：2012-10-25
申请号：US13093742
申请日：2011-04-25
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L23/485 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
摘要翻译：具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。保护屏障形成在电介质间隔物上。导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

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