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1. 发明申请

US20080093663A1 Nonvolatile memory device and method for forming the same 审中-公开
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20080093663A1
公开(公告)日：2008-04-24
申请号：US11882654
申请日：2007-08-03
申请人： Jang-hee Lee , Gil-Heyun Choi , Byung-hee Kim , Tae-Ho Cha , Hee-Sook Park , Geum-Jung Seong
发明人： Jang-hee Lee , Gil-Heyun Choi , Byung-hee Kim , Tae-Ho Cha , Hee-Sook Park , Geum-Jung Seong
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the substrate, forming a barrier metal layer on the polysilicon pattern and on the third insulating pattern, forming a conductive layer on the barrier metal layer, patterning the conductive layer to simultaneously form a first conductive pattern on the polysilicon pattern and a second conductive pattern on the third insulating pattern, and patterning the barrier metal layer to simultaneously form a first barrier metal pattern on the polysilicon pattern and a second barrier metal pattern on the third insulating pattern.
摘要翻译：形成存储器件的方法包括在衬底的周边区域中形成第一绝缘图案和多晶硅图案，在单元中形成包括第二绝缘图案，电荷存储图案和第三绝缘图案的单元栅极绝缘图案在所述多晶硅图案和所述第三绝缘图案上形成阻挡金属层，在所述阻挡金属层上形成导电层，图案化所述导电层以同时在所述多晶硅图案上形成第一导电图案，并且将第二导电图案化所述阻挡金属层，同时在所述多晶硅图案上形成第一阻挡金属图案，以及在所述第三绝缘图案上形成第二阻挡金属图案。

2. 发明授权

US07518214B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07518214B2
公开(公告)日：2009-04-14
申请号：US11586610
申请日：2006-10-26
申请人： Dong-chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
发明人： Dong-chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
IPC分类号： H01L29/00
CPC分类号： H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4941 , H01L29/517 , H01L29/518 , H01L29/6656
摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.
摘要翻译：半导体器件的集成电路具有不易发生严重RC延迟的线型图案。该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。集成电路可以构成半导体器件的栅极线。集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

3. 发明申请

US20070099365A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070099365A1
公开(公告)日：2007-05-03
申请号：US11586610
申请日：2006-10-26
申请人： Dong-Chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
发明人： Dong-Chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
IPC分类号： H01L21/8234
CPC分类号： H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4941 , H01L29/517 , H01L29/518 , H01L29/6656
摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.
摘要翻译：半导体器件的集成电路具有不易发生严重RC延迟的线型图案。该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。集成电路可以构成半导体器件的栅极线。集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

4. 发明申请

US20080200031A1 Method of fabricating gate electrode having polysilicon film and wiring metal film 审中-公开
标题翻译：制造具有多晶硅膜和布线金属膜的栅电极的方法
公开(公告)号：US20080200031A1
公开(公告)日：2008-08-21
申请号：US12007999
申请日：2008-01-18
申请人： Jang-hee Lee , Tae-ho Cha , Hae-sook Park , Gil-heyun Choi , Byung-hee Kim
发明人： Jang-hee Lee , Tae-ho Cha , Hae-sook Park , Gil-heyun Choi , Byung-hee Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78
摘要： A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer.
摘要翻译：根据示例实施例的形成半导体器件的栅电极的方法，其可以包括在半导体衬底上形成多晶硅膜。可以通过多次重复单位周期在多晶硅膜上形成界面控制层。单元循环可以包括形成界面金属膜并氮化界面金属膜的上表面部分以在界面金属膜的上表面部分上形成界面金属氮化物膜。可以在界面控制层上形成布线金属膜。

5. 发明申请

US20090101984A1 Semiconductor device having gate electrode including metal layer and method of manufacturing the same 审中-公开
标题翻译：具有包括金属层的栅电极的半导体器件及其制造方法
公开(公告)号：US20090101984A1
公开(公告)日：2009-04-23
申请号：US12003144
申请日：2007-12-20
申请人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
发明人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28247
摘要： A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film.
摘要翻译：半导体器件可以包括在半导体衬底和/或栅电极上的栅极电介质膜。栅电极可以包括依次层叠在栅极电介质膜上的第一金属膜，第一金属硅化物膜和/或导电多晶硅膜。

6. 发明申请

US20060292784A1 Methods of Forming Integrated Circuit Devices Including Memory Cell Gates and High Voltage Transistor Gates Using Plasma Re-Oxidation 审中-公开
标题翻译：使用等离子体再氧化形成包括存储单元门和高压晶体管门的集成电路器件的方法
公开(公告)号：US20060292784A1
公开(公告)日：2006-12-28
申请号：US11424995
申请日：2006-06-19
申请人： Woong Sohn , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Tae-ho Cha
发明人： Woong Sohn , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Tae-ho Cha
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/321 , H01L21/823437 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11531
摘要： A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is annealed and the annealed semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is plasma oxidized.
摘要翻译：形成集成电路器件的方法可以包括在半导体衬底的外围电路区域中的半导体衬底的存储单元区域和多个高压晶体管栅极中形成多个堆叠的单元栅极。包括多个堆叠的单元栅极和多个高压晶体管栅极的半导体基板被退火，并且包括多个堆叠的单元栅极和多个高压晶体管栅极的退火的半导体衬底被等离子体氧化。

7. 发明授权

US07897500B2 Methods for forming silicide conductors using substrate masking 有权
标题翻译：使用基板掩模形成硅化物导体的方法
公开(公告)号：US07897500B2
公开(公告)日：2011-03-01
申请号：US12276562
申请日：2008-11-24
申请人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
发明人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28052 , H01L29/66545
摘要： A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
摘要翻译：多个间隔开的导体结构形成在半导体衬底上，每个导体结构包括导电层。绝缘垫片形成在导体结构的侧壁上。形成填充相邻绝缘间隔件之间的间隙的层间绝缘膜。去除层间绝缘层的一部分以暴露导电层的上表面。相应的外延层在导电层的相应暴露的上表面上生长，并且各自的外延层形成各自的金属硅化物层。

8. 发明申请

US20090191699A1 METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING 有权
标题翻译：使用基板掩模形成硅胶导体的方法
公开(公告)号：US20090191699A1
公开(公告)日：2009-07-30
申请号：US12276562
申请日：2008-11-24
申请人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
发明人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L29/66545
摘要： A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
摘要翻译：多个间隔开的导体结构形成在半导体衬底上，每个导体结构包括导电层。绝缘垫片形成在导体结构的侧壁上。形成填充相邻绝缘间隔件之间的间隙的层间绝缘膜。去除层间绝缘层的一部分以暴露导电层的上表面。相应的外延层在导电层的相应暴露的上表面上生长，并且各自的外延层形成各自的金属硅化物层。

9. 发明授权

US08486783B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08486783B2
公开(公告)日：2013-07-16
申请号：US12658520
申请日：2010-02-11
申请人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
发明人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/456 , H01L29/66666
摘要： A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.
摘要翻译：一种制造半导体器件的方法包括：通过蚀刻衬底形成用于形成掩埋型线的沟槽; 在沟槽的底部和沟槽的壁上分别形成第一和第二氧化层; 去除一部分第一氧化层和整个第二氧化层; 以及通过在去除所述第二氧化层的所述沟槽的壁上执行硅化物处理，在所述沟槽的壁上形成所述埋入式导线。结果，埋入式电线彼此绝缘。

10. 发明申请

US20100240185A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100240185A1
公开(公告)日：2010-09-23
申请号：US12658520
申请日：2010-02-11
申请人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
发明人： Woong-hee Sohn , Byung-hee Kim , Dae-yong Kim , Min-sang Song , Gil-heyun Choi , Kwang-jin Moon , Hyun-su Kim , Jang-hee Lee , Eun-ji Jung , Eun-ok Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/456 , H01L29/66666
摘要： A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.
摘要翻译：一种制造半导体器件的方法包括：通过蚀刻衬底形成用于形成掩埋型线的沟槽; 在沟槽的底部和沟槽的壁上分别形成第一和第二氧化层; 去除一部分第一氧化层和整个第二氧化层; 以及通过在去除所述第二氧化层的所述沟槽的壁上执行硅化物处理，在所述沟槽的壁上形成所述埋入式导线。结果，埋入式电线彼此绝缘。

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